Semiconductor Package Wiring Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor packages face challenges in maintaining signal integrity and power integrity due to increasing data transmission speeds, which can lead to slope distortion, phase distortion, and reduced data transmission speeds.
Innovation Solution
The semiconductor package includes a substrate with conductive lines, bonding fingers, and a wiring circuit region, where the wiring circuit region has a conductive layer and an insulating layer disposed at the same height level, and a through-hole overlapping the bonding fingers in the vertical direction, which reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission speed is increased, then communication performance is improved, but signal integrity deteriorates due to slope distortion and phase distortion
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitance formed between bonding fingers and conductive lines by introducing a via hole that connects these overlapping conductive elements to a ground layer, thereby eliminating the source of signal distortion while maintaining high data transmission speeds
Solution Approach 2:
The patent introduces a via hole as an intermediary element that provides a ground connection path between the overlapping bonding fingers and conductive lines, mediating the electromagnetic interference and preventing parasitic capacitance from degrading signal integrity at high transmission speeds
2Device complexity
If bonding fingers and conductive lines are arranged to overlap, then wiring density is improved, but parasitic capacitance increases causing signal quality degradation
Solution Approach 1:
The patent converts the harmful parasitic capacitance effect into a beneficial grounded structure by using the via hole to connect the overlapping bonding fingers and conductive lines to the ground layer, transforming the harmful electromagnetic coupling into a controlled ground reference that improves signal quality while maintaining wiring density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the quality of transmitted/received signals and power by reducing parasitic capacitance, thereby enhancing signal integrity, power integrity, and data transmission speed.
Implementation Method 1
the conductive layer and the portion of the insulating layer are disposed at a first height level, and the conductive layer and the portion of the insulating layer are coplanar with each other. The portion of the insulating layer overlaps the bonding fingers in a vertical direction
Implementation Method 2
The through-opening overlaps the bonding fingers in a vertical direction. The bonding fingers are arranged repeatedly in a row in a first direction. A length of the through-opening in the first direction is longer than a length of the through-opening in a second direction, perpendicular to the first direction
Data Source
AI summary
A semiconductor package includes a substrate including terminals and a first conductive layer electrically connected to the terminals, bonding wires having one ends electrically connected to the terminals, and a semiconductor chip on an upper side of the substrate and having a structure in which pads electrically connected to other ends of the bonding wires are disposed on an upper surface. The substrate further includes a second conductive layer overlapping a portion of the wiring circuit layer in a vertical direction, and the lower conductive layer includes a through-hole in a region overlapping the terminals in the vertical direction.