Semiconductor Package Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing semiconductor device packages face challenges in minimizing parasitic capacitance and optimizing the layout of source and drain pads, which affects the efficiency and size of field effect transistors.
Innovation Solution
A semiconductor device package design featuring a substrate with a transistor, lead frame, and specific pad configurations, including source and drain pads with controlled overlapping areas and via holes, to reduce parasitic capacitance and enhance electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source pad and drain pad are designed with large bonding areas to facilitate external circuit bonding, then the ease of manufacture and electrical connection are improved, but the parasitic capacitance of the field effect transistor increases and the device area increases
Solution Approach 1:
The source pad is designed to extend in the vertical direction above the drain electrode, creating a three-dimensional overlapping structure. This dimensional change allows the pad to achieve adequate bonding area while minimizing the horizontal footprint and reducing parasitic capacitance between source and drain regions.
Solution Approach 2:
The source pad is divided into multiple segments: a first source pad portion at the same level as the drain electrode and a second source pad portion extending above the drain electrode. This segmentation allows different portions to serve different functions - one for electrical connection and another for bonding, thereby reducing overall parasitic capacitance while maintaining bonding area.
2Area of stationary object
If the source pad and drain pad are placed close to each other to minimize device area, then the area of the field effect transistor is reduced, but the parasitic capacitance between source and drain increases
Solution Approach 1:
By extending the source pad vertically above the drain electrode rather than placing it horizontally adjacent to the drain pad, the design achieves compact footprint while minimizing the overlapping area between source and drain regions, thus reducing parasitic capacitance.
Solution Approach 2:
The source pad structure is designed asymmetrically with respect to the drain electrode, extending vertically above it rather than being positioned symmetrically beside it. This asymmetric configuration optimizes space utilization while controlling parasitic capacitance.
3Device complexity
If the lead frame is electrically connected to the gate electrode directly, then the electrical connection is simplified, but the parasitic capacitance between the lead frame and the transistor increases
Solution Approach 1:
An inter-insulating layer is introduced as an intermediary between the lead frame and the substrate, which electrically isolates the lead frame from the transistor while maintaining mechanical support. This intermediary structure reduces parasitic capacitance between the lead frame and the transistor components.
Solution Approach 2:
The electrical connection between the lead frame and the gate electrode is extracted from a direct connection and routed through external terminals and bonding wires, separating the mechanical support function from the electrical connection function to minimize parasitic capacitance.
Data Source
AI summary
A semiconductor device package includes a substrate, a transistor, and a lead frame disposed on a side of the substrate opposite to the transistor. The transistor is disposed on the substrate, and includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, a first drain pad, a source plug, and a drain plug. The source and the drain electrodes are disposed on the active layer. An orthogonal projection of the source electrode on the active layer forms a source region. The first insulating layer covers at least a portion of the source electrode and at least a portion of the drain electrode. The first source pad and the first drain pad are disposed on the first insulating layer. An orthogonal projection of the first source pad on the active layer forms a source pad region overlaps the drain region.