Semiconductor Package Parasitic Conduction Mitigation
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Solution Overview
Problem
Miniaturized active integrated circuit packages in high-frequency applications, such as those for 5G millimeter wave technology, face significant parasitic surface conduction issues due to charge separation in insulating layers, leading to parasitic currents and cross-talk between adjacent dies, which existing high resistance silicon substrates like SOI cannot effectively resolve.
Innovation Solution
A semiconductor package structure is designed with a substrate, a die electrically connected to the substrate, and a first encapsulant between the substrate and the die's front surface, where the bulk silicon layer underneath the insulating layer is removed to cut off parasitic current paths, and an encapsulant is used to support and protect the antenna structure, reducing parasitic surface conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturized active integrated circuit packages are used for 5G millimeter wave applications, then device size is reduced and bandwidth is improved, but parasitic surface conduction increases causing cross-talk between adjacent dies
Solution Approach 1:
The patent removes the bulk silicon layer underneath the insulating layer to extract and eliminate the parasitic current path. By taking out the problematic silicon substrate that causes charge separation and surface conduction, the harmful parasitic effects are eliminated while maintaining the miniaturized package structure's benefits.
Solution Approach 2:
The patent introduces an intermediary encapsulant material to replace the bulk silicon layer. This encapsulant acts as a mediator that provides mechanical support and protection while preventing charge separation and parasitic conduction, thus resolving the cross-talk issue between adjacent dies in miniaturized packages.
2Reliability
If high resistance silicon substrate like SOI is used, then parasitic surface conduction is reduced, but it can no longer resolve the problems caused by parasitic surface conduction in millimeter wave applications
Solution Approach 1:
The patent fundamentally changes the structural parameter of the substrate by removing the bulk silicon layer entirely, rather than merely adjusting resistance parameters. This structural transformation eliminates the charge separation mechanism at the silicon-oxide interface, making the solution effective for millimeter wave applications where SOI technology fails.
3Object-generated harmful factors
If bulk silicon layer is removed to cut off parasitic current paths, then parasitic surface conduction is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent performs the bulk silicon layer removal as a preliminary action during wafer fabrication, before die attachment and packaging. By removing the silicon layer at the wafer level in advance, the parasitic current paths are eliminated before the devices are assembled, simplifying the overall manufacturing process compared to attempting to address parasitic conduction after packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes parasitic surface conduction, enhancing the performance of high resistance active integrated circuits by eliminating the parasitic current path through the silicon and silicon oxide layers, thereby reducing cross-talk and improving the reliability of miniaturized active integrated circuits in high-frequency applications.
Implementation Method 1
removing the bulk silicon layer by a wafer-level etching operation
Data Source
AI summary
A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.