Semiconductor Package Passive Element Height Stratification
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Solution Overview
Problem
The challenge is to miniaturize semiconductor packages while maintaining high functionality, as mounting high functional elements increases the package height and size, and achieving sufficient bonding margins requires a wide ball pitch, further enlarging the package.
Innovation Solution
A semiconductor package design that incorporates a substrate with semiconductor chips and passive elements, where taller second passive elements are strategically placed to reduce the overall height and size, including capacitors, resistors, inductors, and tantalum capacitors, and uses a sealing member and under-fill material for bonding and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high functional elements are mounted on the substrate, then the functionality of the semiconductor package is improved, but the height and size of the package increase
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional vertical stacking, where passive elements are arranged in multiple layers above the substrate. This dimensional change allows high functionality to be achieved without increasing the horizontal footprint, and enables better control over package height through vertical integration rather than lateral expansion.
Solution Approach 2:
The patent implements a nested structure where passive elements are embedded within and around the semiconductor chip assembly. Taller passive elements are positioned to pass through openings in the upper package, while shorter elements are integrated within the substrate or lower package layers, creating a compact nested arrangement that maximizes functionality within minimal height constraints.
2Reliability
If a wide ball pitch is used to obtain sufficient bonding margin, then the bonding reliability is improved, but the size of the semiconductor package increases
Solution Approach 1:
The patent moves bonding connections from a two-dimensional planar arrangement to a three-dimensional vertical configuration. Solder balls and connection structures are distributed across multiple height levels, allowing sufficient bonding margins to be achieved through vertical separation rather than horizontal spacing, thereby reducing the overall package footprint while maintaining bonding reliability.
3Length of stationary object
If passive elements are embedded in the substrate to reduce height, then the package size is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent divides passive elements into distinct height categories (taller and shorter elements) and assigns them to different spatial zones and mounting sequences. This segmentation simplifies the manufacturing process by allowing standardized mounting operations for each type, rather than requiring complex custom integration for each individual element, thereby reducing overall manufacturing complexity while achieving compact height.
Data Source
AI summary
A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.