Semiconductor Package With Embedded Passive Elements
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Solution Overview
Problem
The semiconductor industry faces challenges in creating high-density, small-sized semiconductor packages with improved power integrity characteristics, particularly in integrating passive elements effectively within these packages.
Innovation Solution
A method of fabricating semiconductor packages involves stacking a lower semiconductor chip on a substrate, forming a molding layer, and using laser drilling to create connecting and element through-holes, allowing passive elements to be inserted between the chip and the connecting through-holes, which are bonded to both the lower and upper package substrates for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive elements are mounted on semiconductor packages to improve power integrity characteristic, then power integrity is improved, but package height increases
Solution Approach 1:
The patent embeds passive elements inside through-holes of the package substrate, nesting them within the existing package structure rather than mounting them on the surface. This allows passive elements to be integrated into the substrate thickness, improving power integrity without significantly increasing overall package height
Solution Approach 2:
The patent transitions from surface-mounting passive elements (2D placement) to embedding them within the substrate thickness (3D integration). By utilizing the vertical dimension of the substrate and creating through-holes, the design integrates passive elements in the Z-direction, achieving better power integrity while maintaining compact package dimensions
2Adaptability or versatility
If multiple passive elements are integrated into the package, then power integrity and functionality are improved, but device complexity increases
Solution Approach 1:
The package substrate is designed with multi-functionality, serving both as the structural platform for mounting semiconductor chips and as the integration medium for passive elements. The through-holes in the substrate simultaneously provide mechanical support, electrical interconnection, and housing for passive components, reducing overall device complexity despite multiple integrated elements
Solution Approach 2:
The patent combines multiple functions into the package substrate: mechanical support structure, electrical interconnection pathway, and passive element housing. By merging these functions into a single integrated substrate design rather than separate components, the overall device complexity is reduced even though multiple passive elements are incorporated
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of passive elements within the semiconductor package, enhancing power integrity and reducing package height by allowing for efficient electrical connections between the substrates, thus addressing the need for high-density and small-sized semiconductor devices.
Implementation Method 1
forming a connecting through-hole and an element through-hole by performing a laser drilling process on the lower molding layer
Data Source
AI summary
Provided are semiconductor packages and methods of fabricating the same. The method may include, stacking a lower semiconductor chip on a lower package substrate, forming a lower molding layer on the lower package substrate, forming a connecting through-hole and an element through-hole by performing a laser drilling process on the lower molding layer, and stacking an upper package substrate having a bottom surface to which a passive element is bonded on the lower package substrate to insert the passive element into the element through-hole.