Semiconductor Package Passive Element Placement
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Solution Overview
Problem
Conventional BGA type semiconductor devices face limitations in wiring flexibility and increased size due to the restricted placement of passive elements and bonding wires, leading to higher fabrication costs and potential short circuits.
Innovation Solution
A semiconductor package design where passive elements are positioned between the packaging substrate and the semiconductor chip, with an adhesive film sandwiched between the chip and the passive elements, and bonding wires connecting the chip to pads outside the chip mounting area, encapsulated by an encapsulant, allowing for increased flexibility and reduced risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive elements are positioned at corners or outside chip mounting areas to facilitate electrical connection, then electrical connection is achieved, but wiring flexibility is reduced and the number of passive elements is limited
Solution Approach 1:
The patent repositions passive elements from the traditional planar arrangement (corners or outside chip mounting areas) to a vertical arrangement between the substrate and semiconductor chip. This dimensional change from 2D to 3D space allows passive elements to be placed in the z-direction, freeing up the substrate surface for more flexible wiring layouts and increasing the number of passive elements that can be accommodated.
Solution Approach 2:
The patent embeds passive elements within the package structure by positioning them between the substrate and semiconductor chip, effectively nesting them within the package volume. This nesting approach utilizes the vertical space within the package, allowing passive elements to be integrated without increasing the package footprint and enabling more elements to be accommodated.
2Quantity of substance
If surface area of substrate is increased to accommodate more passive elements and semiconductor chips, then capacity increases, but package size increases
Solution Approach 1:
The patent transitions from a 2D planar arrangement of passive elements on the substrate surface to a 3D vertical arrangement between the substrate and chip. This allows the package to accommodate more passive elements by utilizing the vertical dimension, thereby increasing element capacity without expanding the package footprint.
Solution Approach 2:
The patent employs a thin adhesive film to attach passive elements to the substrate and positions the semiconductor chip above them, creating a compact vertical stack. This thin-film approach minimizes the vertical space occupied by each layer, allowing more passive elements to be accommodated within a compact package volume.
3Reliability
If bonding wires are positioned high above passive elements to prevent contact, then short circuits are prevented, but bonding difficulty and processing complexity increase
Solution Approach 1:
The patent introduces an adhesive film as an intermediary layer between the passive elements and the semiconductor chip. This adhesive film acts as a mediator that allows the chip to be positioned close to or in contact with passive elements while preventing direct electrical contact, thereby maintaining short circuit prevention without requiring bonding wires to be positioned high above the passive elements.
Solution Approach 2:
The patent applies an adhesive film to passive elements before mounting the semiconductor chip, creating a preliminary protective barrier that prevents electrical contact between the chip and passive elements. This preliminary anti-action eliminates the need for complex bonding wire routing to prevent short circuits, simplifying the bonding process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances wiring flexibility, reduces the risk of short circuits, and increases product yield and reliability by optimizing the placement of passive elements and bonding wires, while maintaining a compact package size.
Implementation Method 1
an adhesive film attached to the passive elements; a semiconductor chip attached to the adhesive film
Data Source
AI summary
A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring.