Semiconductor Package Layout With High-Density Patch Routing
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in efficiently connecting high-density semiconductor dies while maintaining a low-density substrate routing density, leading to increased costs and potential reliability issues.
Innovation Solution
A semiconductor device design featuring a low-density substrate with embedded low-density pillars and a high-density patch that allows high-density bumps to be directly connected without increasing the substrate's routing density, using a multi-layered redistribution structure to connect high-density circuit patterns directly to high-density bumps, while low-density bumps are connected to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density bumps are connected using conventional substrate routing, then electrical connectivity is achieved, but the substrate routing density increases leading to increased costs and reduced reliability
Solution Approach 1:
The patent introduces a multi-layered redistribution structure that routes high-density bump signals through vertical vias and multiple conductive layers instead of relying solely on planar substrate traces. This dimensional transition from 2D substrate routing to 3D layered routing reduces the substrate routing density while maintaining electrical connectivity, thereby resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent employs a dedicated high-density patch and redistribution layers as intermediary structures between the high-density bumps and the low-density substrate. These intermediary layers handle the complex routing of high-density signals, preventing the substrate itself from becoming congested and maintaining both reliability and low substrate complexity.
2Reliability
If high-density semiconductor dies are connected with high substrate routing density, then electrical connectivity is achieved, but manufacturing costs increase
Solution Approach 1:
The patent segments the routing function into different layers and structures: the substrate provides low-density routing, while a separate multi-layered redistribution structure handles high-density routing. This segmentation allows each layer to be optimized independently, reducing overall manufacturing complexity and cost while maintaining electrical connectivity reliability.
Solution Approach 2:
By transitioning from planar substrate routing to multi-layered vertical routing with vias and conductive layers, the patent reduces the burden on substrate routing density. This dimensional change enables cost-effective manufacturing by using standard substrate technologies for the base layer while adding specialized routing only where high-density connections are required.
3Reliability
If the substrate routing density is increased to connect high-density bumps, then connectivity is improved, but manageability and manufacturing complexity increase
Solution Approach 1:
The patent applies local quality by creating a high-density patch only in specific regions where high-density bump connections are required, while the rest of the substrate maintains low-density routing. This localized approach improves connectivity where needed without increasing overall substrate complexity and manageability, as the low-density areas remain simple and easy to manufacture.
Data Source
AI summary
A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.