Semiconductor Package Structure with Permanent Circuit Substrate

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Solution Overview

Problem

The challenge in semiconductor package technology is to reduce manufacturing costs while maintaining high input/output (I/O) connection numbers and improving electrical performance.

Innovation Solution

A semiconductor package structure that includes a circuit substrate, chips, an encapsulant, conductive connectors, a redistribution layer, and conductive terminals, where the circuit substrate is a permanent substrate, eliminating the need for a temporary carrier substrate and allowing for high I/O connections through the redistribution layer and conductive connectors, thereby reducing manufacturing costs and enhancing electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a temporary carrier substrate is used during manufacturing, then the chip can be properly positioned and processed, but the manufacturing cost increases and additional removal procedures are required

Engineering Contradiction:
Improvemanufacturing costVSAvoidmanufacturing process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The invention extracts and eliminates the temporary carrier substrate from the manufacturing process. The circuit substrate is designed to function as the final permanent substrate rather than a temporary carrier, removing the need for subsequent carrier removal procedures and reducing both cost and process complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The circuit substrate is designed to serve multiple functions: it provides mechanical support for chip mounting, enables electrical connections through conductive connectors, and serves as the final permanent substrate without requiring removal. This multi-functionality eliminates the need for separate temporary carrier substrates

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the number of I/O connections is increased, then the functionality and performance of the semiconductor package is improved, but the manufacturing cost increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention transitions from planar I/O connections to three-dimensional vertical connections using conductive connectors that extend through the encapsulant. This dimensional change allows multiple I/O connections to be achieved without increasing the footprint area, enabling high I/O density while maintaining cost-effectiveness

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The electrical connection path is segmented into multiple independent conductive connectors distributed throughout the encapsulant. Each connector provides separate I/O pathways, allowing the system to achieve high I/O connection numbers through parallel segmented connections rather than requiring a single complex connection structure

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11171106B2Semiconductor package structure with circuit substrate and manufacturing method thereof
Publication Date: 2021.11.09 POWERTECH TECHNOLOGY INC
  • US11171106B2 patent drawing
  • US11171106B2 patent drawing
  • US11171106B2 patent drawing

AI summary

A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.