Semiconductor Package Structure Eliminating Pillar Collisions
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Solution Overview
Problem
Conventional semiconductor package structures face yield reduction due to collisions between bridge dies and tall pillars during bonding, leading to damaged pillars and decreased I/Os, necessitating a new structure that reduces size and enhances connectivity.
Innovation Solution
A semiconductor package structure featuring a lower conductive structure with integrated high-density and low-density circuits, along with conductive vias, which replaces the bridge die and tall pillars, enabling 3D communication and reducing overall size by integrating these components within the upper conductive structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tall pillars are formed on the redistribution layer for electrical connection, then electrical connectivity is achieved, but the bridge die collides with the pillars during bonding causing damage and reduced yield
Solution Approach 1:
The patent extracts the harmful tall pillars from the conventional structure and replaces them with a planarized conductive structure. The redistribution layer is processed to create a flat surface without protruding pillars, eliminating the collision hazard while maintaining electrical connectivity through vias and conductive paths within the planar structure.
Solution Approach 2:
Instead of having pillars protrude upward from the redistribution layer to achieve connection, the patent inverts the approach by creating downward-extending vias and using a planar top surface. The electrical connection is achieved through inverted T-shaped vias that extend into the substrate rather than upward pillars, fundamentally reversing the connection geometry to eliminate collision issues.
2Productivity
If conventional bridge die structure is used with tall pillars, then electrical connection between devices is achieved, but the package size remains large and I/Os are reduced
Solution Approach 1:
The patent merges the functions of separate pillars and bridge die into an integrated planar conductive structure. The redistribution layer, vias, and connection paths are combined into a single planarized structure that provides both mechanical support and electrical connectivity, eliminating the need for separate tall pillars and reducing overall package footprint.
Solution Approach 2:
The patent transitions from a vertical three-dimensional pillar structure to a planar two-dimensional conductive structure. Electrical connections are achieved through lateral routing and via paths within the planar redistribution layer rather than vertical pillar extensions, effectively using dimensional transformation to reduce package height and improve I/O density.
3Ease of manufacture
If tall pillars are formed for electrical connection, then connectivity is achieved, but the structure complexity increases and manufacturing difficulty arises
Solution Approach 1:
The patent performs preliminary planarization of the redistribution layer before subsequent bonding and connection steps. By flattening the surface and pre-forming the conductive paths and vias in advance, the structure is prepared in its final configuration before device attachment, eliminating the need for post-bonding pillar formation or adjustment and simplifying the overall manufacturing sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances yield by preventing pillar damage, reduces package size, and increases I/Os through efficient electrical connectivity between semiconductor devices, addressing the limitations of conventional structures.
Implementation Method 1
bonding the upper conductive structure to the lower conductive structure
Data Source
AI summary
A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a lower conductive structure, a first semiconductor device and a second semiconductor device. The upper conductive structure is disposed on the lower conductive structure. The second semiconductor device is electrically connected to the first semiconductor device by a first path in the upper conductive structure. The lower conductive structure is electrically connected to the first semiconductor device through a second path in the upper conductive structure under the first path.