Semiconductor Package Pillar Layer Integration
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Solution Overview
Problem
The challenge is to reduce the size and manufacturing cost of semiconductor packages while enhancing the performance of 3D graphic processing circuits and extending the operating time of mobile devices by achieving high integration and efficient power consumption.
Innovation Solution
A semiconductor package structure is developed, comprising a package substrate with a first conductive layer, a pillar layer, and a package body, where the pillar layer connects the conductive layers, allowing for the integration of multiple electronic components with reduced thickness and increased electrical connectivity, and a manufacturing method that forms these components using conductive layers and pillar layers with encapsulating materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple packages are integrated in a single semiconductor package (PoP structure), then the size is reduced and high-density system integration is achieved, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the package substrate into multiple distinct layers (first substrate layer, second substrate layer, intermediate layer) with specific functional assignments. Each layer can be manufactured and prepared separately before assembly, reducing overall manufacturing complexity while achieving high-density integration through the stacked configuration.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by integrating multiple packages vertically in a PoP structure. This dimensional change allows high-density system integration without proportionally increasing manufacturing complexity, as each layer can be processed independently before final assembly.
2Volume of moving object
If the package size is reduced for miniaturization, then the integration density increases, but the manufacturing cost increases due to higher integration requirements
Solution Approach 1:
The patent segments the package into multiple manufacturable layers that can be produced using standard semiconductor fabrication processes. This segmentation allows each layer to be optimized independently for cost-effective manufacturing while achieving miniaturization through vertical stacking, thereby reducing the contradiction between small size and manufacturing cost.
Solution Approach 2:
The package substrate structure is designed to serve multiple functions: electrical interconnection between stacked packages, mechanical support for the PoP architecture, and thermal management pathway. This multi-functionality reduces the need for additional specialized components, lowering manufacturing costs while maintaining miniaturization benefits.
3Use of energy by moving object
If multiple electronic components are integrated in a compact structure, then the power consumption is reduced and operating time is extended, but the electrical connectivity requirements become more complex
Solution Approach 1:
The patent divides the electrical interconnection system into discrete conductive layers (first conductive layer, second conductive layer, third conductive layer) with specific routing functions. This segmentation simplifies the design and manufacturing of electrical connectivity paths, making it easier to manage power distribution and signal routing in the compact multi-component structure.
Solution Approach 2:
The package substrate acts as an intermediary structure that provides standardized electrical interconnection interfaces between stacked electronic components. This intermediary layer simplifies the electrical connectivity complexity by providing pre-fabricated connection paths, reducing the need for complex wire bonding or direct component-to-component connections.
Data Source
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AI summary
A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.