Semiconductor Package Layout for High Pin Density and Heat Dissipation
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving compact size and efficient heat dissipation, particularly for small-sized semiconductor chips with a large number of pins, as traditional fan-in packages are limited by spatial constraints and thermal management.
Innovation Solution
A semiconductor package design incorporating a connection structure with redistribution layers, encapsulant, and a heat dissipation element on the second surface, which includes a frame with through-holes and wiring structures to connect the redistribution layers and facilitate heat dissipation, allowing for improved thermal management and compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional fan-in packaging is used, then the package structure is simple, but the package size cannot be reduced and heat dissipation is insufficient
Solution Approach 1:
The patent transitions from planar fan-in packaging to three-dimensional fan-out packaging with multiple redistribution layers at different heights. The first and second redistribution layers are positioned at different vertical levels, with the second layer extending beyond the chip footprint, enabling compact packaging while maintaining simplicity.
Solution Approach 2:
The package structure is divided into distinct functional segments: chip, encapsulant, first redistribution layer, second redistribution layer, and heat dissipation element. This segmentation allows each component to be optimized independently while achieving overall compactness and simplified assembly.
2Quantity of substance
If more pins are implemented in small-sized chips, then pin count increases, but spatial constraints and thermal management become problematic
Solution Approach 1:
The patent uses vertical stacking of redistribution layers to accommodate high pin counts in small chips. The first redistribution layer connects to chip pads, while the second redistribution layer provides additional connection points extending beyond the chip area, enabling increased pin density without increasing chip footprint.
Solution Approach 2:
The patent introduces a heat dissipation element as an intermediary component positioned between the chip and the external environment. This element facilitates thermal management by providing a dedicated heat dissipation path, resolving the thermal constraints that would otherwise limit pin count in small chips.
3Volume of moving object
If fan-out packaging is used, then compact size and large pin count are achieved, but heat dissipation characteristics need improvement
Solution Approach 1:
The patent positions a heat dissipation element as an intermediary between the chip and external environment. This element is configured to receive heat from the chip through the encapsulant and redistribute it, improving heat dissipation characteristics while maintaining the compact fan-out package structure.
Solution Approach 2:
The encapsulant serves multiple functions: it provides mechanical support, electrical insulation, and thermal conduction pathways to the heat dissipation element. This multi-functionality allows the same component to address both structural and thermal management requirements of compact fan-out packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances heat dissipation capabilities while maintaining a compact size, enabling the use of small-sized semiconductor chips with a large number of pins without the need for interposer substrates, thus addressing spatial and thermal limitations of traditional packages.
Implementation Method 1
a heat dissipation element disposed on at least a portion of the second surface of the connection structure
Data Source
AI summary
A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.