Power Semiconductor Package Locking Mechanism for Pin Stability
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Solution Overview
Problem
Conventional power semiconductor package devices face challenges in reducing size due to cutting process variations, leading to potential pad exposure and detachment issues, especially with the gate and source pads being close to the edges, which can result in safety concerns during mounting.
Innovation Solution
The solution involves exposing the bottom and side surfaces of the gate and source pins from the plastic package body and incorporating recess areas at the corners of these pins, along with a molding compound to secure them in place, preventing detachment during the cutting process and allowing for a reduced package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate pad and source pad are located very close to edges of the package device to reduce size, then the package dimension is reduced, but the pads may easily fall off due to cutting process variations
Solution Approach 1:
The patent applies preliminary action by forming recess areas at the corners of the gate pin and source pin before the cutting process. These recess areas are prepared in advance to receive molding compound that will lock the pins in place, preventing them from falling off during subsequent cutting operations despite being positioned close to the package edges.
Solution Approach 2:
The molding compound acts as an intermediary material that fills the recess areas and mechanically locks the gate pin and source pin to the lead frame. This intermediary substance provides the necessary attachment stability without requiring the pads to be positioned far from the package edges, thus resolving the contradiction between miniaturization and reliability.
2Area of stationary object
If the space between gate pad and source pad is reduced to minimize package footprint, then the device fits in smaller mounting space, but safety is compromised due to potential coupling and lapping with soldering paste
Solution Approach 1:
The recess areas are formed at the corners of the pins before mounting, creating a pre-prepared locking structure. This preliminary action ensures that even when pins are positioned close together to minimize footprint, the molding compound will prevent soldering paste from causing coupling or lapping between adjacent pins during the soldering process.
3Productivity
If cutting process is performed to separate individual package devices from semiconductor wafer, then productivity is improved, but size variation is introduced leading to pad exposure and detachment
Solution Approach 1:
The patent applies beforehand cushioning by creating recess areas that will be filled with molding compound before the cutting process. This pre-prepared structure cushions against the size variations introduced during cutting, ensuring that pads remain securely positioned even when cutting precision varies, thus maintaining both productivity and manufacturing precision.
Data Source
AI summary
A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off. Therefore, the size of the power semiconductor package device is reduced.