Semiconductor Package Pin-Through Substrate Layout for Stable Thin Packaging
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Solution Overview
Problem
Semiconductor packages using flip chip bonding face challenges such as tilting of semiconductor chips, which can lead to molding material entering the space between the chip and the upper chip, compromising structural stability and electrical properties.
Innovation Solution
The semiconductor package includes a package substrate with insertion holes that expose wiring patterns, allowing connection pins on the semiconductor chip to directly connect to the substrate's wiring patterns, thereby enhancing structural stability and electrical properties without using bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If flip chip bonding is used to reduce package height and improve electrical characteristics, then package height is reduced and electrical characteristics are improved, but semiconductor chip tilting occurs which allows molding material to enter the space between chips
Solution Approach 1:
The patent applies preliminary action by forming a recess in the semiconductor chip before the molding process, and pre-filling this recess with molding material. This preliminary preparation prevents molding material from entering the space between tilted chips during subsequent packaging processes, thereby maintaining chip positioning stability while still benefiting from the reduced package height of flip chip bonding
Solution Approach 2:
The patent applies preliminary anti-action by creating a countermeasure (the recess filled with molding material) before the harmful effect occurs. The filled recess acts as a barrier that prevents molding material from infiltrating the gap between tilted chips, counteracting the instability caused by chip tilting before it can compromise the package structure
2Length of stationary object
If connection pins are made smaller to reduce package thickness, then routing space is minimized and electrical characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by optimizing the diameter ratio between insertion holes and connection pins. By setting the insertion hole diameter to be larger than the connection pin diameter (with specific ratio ranges), the design allows for smaller connection pins that reduce package thickness while maintaining manufacturability through appropriate tolerance design and alignment margins
Data Source
AI summary
A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip.