Semiconductor Package Planar Bonding for Irregular Chip Stacks
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Solution Overview
Problem
The die-to-wafer bonding process for multichip semiconductor packages faces challenges in properly bonding the uppermost die due to irregular surfaces, leading to potential voids and incomplete bonding.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip with bonding layers and through vias, a stacked chip structure with additional bonding layers, a molding layer surrounding the chip stack, and a dummy semiconductor chip bonded to a fifth bonding layer with a wavy lower surface to ensure proper bonding despite irregular upper surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a die-to-wafer bonding process is used to fabricate a multichip package with stacked semiconductor chips, then the integration density and electrical connection between chips are improved, but the uppermost die cannot be properly bonded or voids are generated when the surface of the die below is rugged or irregular
Solution Approach 1:
A planarization layer is formed over the stacked semiconductor chips before bonding the uppermost die. This preliminary planarization action creates a flat bonding surface that compensates for the ruggedness or irregularities of the underlying chip surfaces, ensuring proper contact and bonding area for the uppermost die while maintaining the stacked configuration.
2Productivity
If multiple semiconductor chips are stacked to increase integration density, then the functional capability and connection efficiency are improved, but the surface irregularities accumulate and prevent proper bonding of upper layers
Solution Approach 1:
The planarization layer is applied preliminarily over the stacked chips before the final bonding process. This allows the stacked configuration to be maintained for high integration density while the planarization layer provides a uniformly flat surface that ensures complete bonding contact for subsequent die attachment.
Solution Approach 2:
The planarization layer acts as an intermediary between the rugged stacked chip surfaces and the uppermost die. It mediates the interface by providing a flat bonding surface that ensures proper contact area and bonding quality without requiring the underlying chips to have perfectly flat surfaces.
3Reliability
If the upper surface of a die is rugged or irregular, then the bonding process becomes difficult and voids are generated, but flattening the surface may require additional processing steps
Solution Approach 1:
Rather than attempting to flatten the rugged surfaces of the stacked chips through complex processing, a planarization layer is introduced as an intermediary. This layer is deposited over the irregular surfaces and provides a flat bonding interface, avoiding the need for complex surface preparation steps while ensuring high bonding quality.
Solution Approach 2:
The solution changes the parameter of surface flatness not by modifying the underlying chip surfaces, but by adding a layer with controlled flatness properties. This parameter change approach allows the bonding surface to be flat without requiring complex processing of the original chip structures.
Data Source
AI summary
A semiconductor package and a method of fabricating the same are provided. The semiconductor package includes a first semiconductor chip; a chip stack including a plurality of second semiconductor chips, which are stacked on the first semiconductor chip; a first molding layer in contact with an upper surface of the first semiconductor chip and side surfaces of the chip stack and exposing an upper surface of the chip stack; a bonding layer in contact with an upper surface of the first molding layer and the upper surface of the chip stack; a dummy semiconductor chip on the bonding layer; and a second molding layer on at least part of the dummy semiconductor chip and on the bonding layer, wherein the upper surface of the chip stack has a wavy shape, and an upper surface of the bonding layer is flat.