Semiconductor Package Planarization for Reliable Electrical Connections
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Solution Overview
Problem
Ensuring the reliability of wafer level packaging in semiconductor devices, which is crucial for electronic apparatus like cell phones, remains a challenge due to variations in manufacturing processes and material compatibility.
Innovation Solution
A method involving the use of a temporary carrier with an adhesive layer and de-bonding layer for die placement, followed by encapsulation, redistribution structure formation, and underfill layer application, along with patterned dielectric and conductive terminal formation to enhance electrical connections and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level packaging is used to improve productivity and reduce cost, then manufacturing efficiency is improved, but reliability and consistency of electrical connections deteriorate due to process variations
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer before conducting bumps to create a flat surface that compensates for underlying topography variations. This pre-preparation ensures that subsequent electrical connections are made on a uniform surface, improving reliability while maintaining wafer-level packaging efficiency
Solution Approach 2:
The patent changes the physical state and properties of materials through controlled processes. The planarization layer undergoes curing to transform from a viscous state to a solid state, and its thickness is precisely controlled to achieve the desired flatness. These parameter changes enable reliable electrical connections despite process variations in wafer-level packaging
2Reliability
If multiple layers and materials are used to improve structural integrity and electrical connections, then reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple functions into the planarization layer: it provides mechanical support, creates surface flatness, and serves as an adhesive layer for conducting bumps. This consolidation reduces the number of separate manufacturing steps and materials needed, lowering complexity while maintaining structural integrity
Solution Approach 2:
The planarization layer is designed to perform multiple functions simultaneously: structural support, surface planarization, and electrical connection substrate. This multi-functionality reduces the overall device complexity by eliminating the need for separate components for each function
3Reliability
If conducting bumps are formed to improve electrical connections, then electrical conductivity is improved, but manufacturing precision requirements increase due to topography variations
Solution Approach 1:
The planarization layer is formed and cured before the conducting bumps are created, establishing a flat surface in advance. This preliminary action eliminates the need for high precision during bump formation, as the bumps are deposited on a uniform surface rather than a varying topography
Solution Approach 2:
The planarization layer acts as an intermediary between the uneven underlying structure and the conducting bumps. It mediates the topography variations by providing a flat intermediate surface, allowing bumps to be formed with standard precision without being affected by underlying irregularities
4Strength
If underfill layer is applied to improve structural stability, then mechanical strength is improved, but process complexity and manufacturing time increase
Solution Approach 1:
The underfill layer is combined with the encapsulant material, eliminating the need for separate application steps. The encapsulant serves dual purposes: protecting the device and providing underfill functionality for mechanical support and stress relief, thereby reducing process complexity while maintaining strength
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.