Semiconductor Package Plate Layout for Crack and Noise Control
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Solution Overview
Problem
Existing semiconductor packages face challenges in suppressing cracks in external connection terminals and canceling noise, particularly due to the uneven stress distribution and increased complexity with highly integrated semiconductor chips.
Innovation Solution
The semiconductor package incorporates a redistribution layer with uniformly arranged external connection terminals and includes a bypass capacitor formed by conductive plates to mitigate noise, ensuring robust connection reliability and noise cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external connection terminals are densely arranged to support highly integrated semiconductor chips, then the chip capacity and I/O connection terminals increase, but stress distribution becomes uneven leading to cracks in external connection terminals
Solution Approach 1:
The patent introduces a vertical dimension by forming plate groups that extend in the thickness direction of the substrate. This three-dimensional arrangement allows stress to be distributed not only in the horizontal plane but also vertically, preventing crack propagation in the external connection terminals while maintaining high I/O density.
Solution Approach 2:
The patent employs a composite structure combining plates extending in different directions (first direction plates and second direction plates) within the plate groups. This composite arrangement creates a reinforcement network that distributes stress uniformly across the substrate, preventing cracks while supporting high integration density.
2Object-generated harmful factors
If plate groups are added to the redistribution layer, then noise cancellation capability improves, but device complexity increases
Solution Approach 1:
The plate groups serve multiple functions simultaneously: they act as mechanical reinforcement to prevent cracks in external connection terminals, function as bypass capacitors for noise cancellation, and provide electrical connection pathways. This multi-functionality reduces the need for separate components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the noise cancellation function with the existing redistribution layer structure by integrating plate groups into the same layer. Instead of adding separate noise cancellation components, the plates are combined with the redistribution conductors, reducing overall structural complexity while achieving both reinforcement and noise filtering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the occurrence of cracks in external connection terminals by distributing stress uniformly and enhances noise cancellation through the strategic placement and design of the bypass capacitor, thereby improving the overall reliability and performance of the semiconductor package.
Implementation Method 1
a bypass capacitor formed by conductive plates to mitigate noise
Data Source
AI summary
A semiconductor package includes: a lower redistribution layer; a semiconductor chip on an upper surface of the lower redistribution layer, the semiconductor chip having an area that is less than an area of the lower redistribution layer; at least one plate group on the upper surface of the lower redistribution layer, each of the at least one plate group including a plurality of conductive plates facing each other and extending in a same direction; and a molding layer covering the upper surface of the lower redistribution layer and surrounding the semiconductor chip and the at least one plate group, wherein the plurality of conductive plates extend along a plane on the upper surface of the lower redistribution layer in a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and each of the plurality of conductive plates has a length in the first horizontal direction that is greater than a length in the second horizontal direction.