Semiconductor Package Insulation Layer Against Plating Solution Bleed

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Solution Overview

Problem

In semiconductor devices, foreign matter can get trapped between the adhesive layer and the semiconductor element, creating gaps that allow plating solutions to bleed in during wiring formation, affecting the device's quality.

Innovation Solution

A semiconductor device design featuring a substrate with an adhesive layer, a semiconductor element adhered to it, through holes exposing electrodes, via wiring connecting these electrodes, and a protective insulation layer covering the semiconductor element's side surfaces and part of its lower surface to prevent plating solution ingress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the semiconductor element is adhered to the adhesive layer, then the device structure is formed, but foreign matter may be trapped creating gaps that allow plating solution to bleed in

Engineering Contradiction:
Improveadhesion processVSAvoidproduct quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces a protective insulation layer as an intermediary barrier between the adhesive layer and the semiconductor element. This layer prevents plating solution from directly contacting the semiconductor element through gaps caused by foreign matter, thus maintaining product quality while preserving the simplicity of the adhesion process

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective insulation layer is formed beforehand on the adhesive layer before the semiconductor element is mounted. This preemptive measure creates a protective barrier that cushions against the potential harm of plating solution infiltration through gaps, preventing quality issues before they occur

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If a protective film with recesses is used to cover the semiconductor element, then plating solution ingress is prevented, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveprotection against plating solutionVSAvoidprotection film structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the protective function from the protection film itself and transfers it to a separate protective insulation layer formed on the adhesive layer. This eliminates the need for complex recess structures in the protection film, simplifying the overall device structure while maintaining effective protection against plating solution ingress

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The protective function is segmented into a dedicated protective insulation layer separate from the adhesion and protection film layers. This segmentation allows each layer to perform its specific function without requiring complex integrated structures, reducing overall device complexity

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11869863B2Semiconductor device
Publication Date: 2024.01.09 SHINKO ELECTRIC IND CO LTD
  • US11869863B2 patent drawing
  • US11869863B2 patent drawing
  • US11869863B2 patent drawing

AI summary

A semiconductor device includes a substrate, an adhesive layer formed on a lower surface of the substrate, a semiconductor element adhered to a lower surface of the adhesive layer, a through hole extending through the substrate and the adhesive layer and exposing a first electrode arranged on an upper surface of the semiconductor element, a via wiring formed in the through hole, a wiring layer formed on an upper surface of the substrate and electrically connected to the first electrode through the via wiring, and a protective insulation layer formed on the lower surface of the adhesive layer. The protective insulation layer covers an entirety of all side surfaces of the semiconductor element and a peripheral part of a lower surface of the semiconductor element and exposes a central part of the lower surface of the semiconductor element.