Semiconductor Package Redistribution Structure for Low-Warpage PLP Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The demand for smaller and lighter electronic components in portable devices necessitates the reduction in size and weight of semiconductor packages, which existing technologies have not adequately addressed through panel-level package (PLP) technology, particularly in terms of efficient manufacturing processes and structural reliability.
Innovation Solution
A semiconductor package design featuring a first redistribution structure with upper and lower connection pads, a vertical connection conductor, encapsulant, and a second redistribution structure with insulating layers and connection pads, along with an intermediate connection terminal and insulating adhesive layer, is proposed. This design includes specific manufacturing processes involving detached copper foil carriers to form and separate structures, allowing for efficient assembly and reduced warpage during bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If panel-level package (PLP) technology is used to reduce semiconductor package size and weight, then the size and weight of electronic components are reduced, but manufacturing process efficiency and structural reliability are not adequately addressed
Solution Approach 1:
The manufacturing process is divided into multiple stages: forming first structures on first DCF carrier, forming second structures on second DCF carrier, and then attaching them together. This segmentation allows each stage to be optimized independently, improving overall manufacturing efficiency while maintaining the size reduction benefits of PLP technology.
Solution Approach 2:
The first and second structures are formed in advance on separate DCF carriers before final assembly. This preliminary action enables parallel processing and preparation of components, which streamlines the manufacturing workflow and enhances production efficiency without compromising package compactness.
2Weight of moving object
If panel-level package (PLP) technology is used to reduce semiconductor package size and weight, then the size and weight of electronic components are reduced, but structural reliability is not adequately addressed
Solution Approach 1:
The patent employs asymmetric design in the bonding process by using different configurations for first and second structures, including strategic placement of connection pads and conductors. This asymmetric arrangement optimizes stress distribution and enhances structural reliability while maintaining compact dimensions.
Solution Approach 2:
The insulating adhesive layer serves as an intermediary between the second redistribution structure and the encapsulant, providing both mechanical bonding and electrical insulation. This intermediary element enhances package reliability by ensuring stable connections and preventing electrical interference in the compact PLP structure.
3Productivity
If detached copper foil method is used to form symmetric structures, then manufacturing efficiency is improved and warpage is minimized, but process complexity increases
Solution Approach 1:
The use of separate first and second DCF carriers divides the manufacturing process into distinct segments, allowing each carrier to be processed independently. This segmentation simplifies the overall process despite the additional steps, as each segment can be optimized and controlled separately, improving manufacturing efficiency while managing complexity.
Solution Approach 2:
The patent utilizes parameter changes in the bonding process, such as temperature and pressure control during attachment of first and second structures, to minimize warpage. By carefully adjusting these parameters, the process achieves high manufacturing efficiency and structural integrity without requiring excessively complex process steps.
4Reliability
If low-temperature solder is used for bonding, then warpage and peeling issues are minimized, but bonding strength may be reduced
Solution Approach 1:
The patent employs composite material strategies by combining low-temperature solder with insulating adhesive layers and carefully selected redistribution structure materials. This composite approach maintains bonding reliability while minimizing warpage, and the overall structure compensates for any reduction in individual bond strength through distributed connection points and optimized material properties.
Data Source
AI summary
A semiconductor package includes: a first redistribution structure including a first upper connection pad and a first lower connection pad; a first semiconductor device on the first redistribution structure; a vertical connection conductor on the first redistribution structure; an encapsulant adjacent to the first semiconductor device; a second redistribution structure on the encapsulant and including a second redistribution pattern, a second insulating layer, a second upper connection pad, and a second lower connection pad; an insulating adhesive layer between the second redistribution structure and the encapsulant; and an intermediate connection terminal connecting the second lower connection pad with the vertical connection conductor, wherein the second upper connection pad is exposed by an upper opening of the second insulating layer. A cover conductive layer is on the second upper connection pad. A side surface of the intermediate connection terminal is covered with the insulating adhesive layer and the encapsulant.