Semiconductor Package Structure for High-Voltage Potential Separation
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Solution Overview
Problem
The existing Intelligent Power Module (IPM) packaging technologies face challenges in maintaining high-voltage spacing between chip holders with different potentials, leading to increased package area, manufacturing complexity, and poor heat dissipation due to the division of the lead frame.
Innovation Solution
A package structure that uses multiple carriers with interconnect structures and insulating layers to maintain voltage differences, allowing for efficient heat dissipation and reduced routing complexity by integrating active and passive components, and enabling the integration of external components around chip holders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lead frame is divided into chip holders with different potentials, then high-voltage spacing is maintained, but the package area increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar lead frame structure to a three-dimensional carrier structure with multiple layers. Different potential chip holders are arranged in vertical stacks rather than being spread out horizontally, maintaining high-voltage spacing through vertical separation while reducing the horizontal package area. The carrier structure utilizes Z-direction stacking to accommodate multiple potentials within a compact footprint.
Solution Approach 2:
The patent implements a nested arrangement where chip holders of different potentials are stacked vertically within the same horizontal footprint. Multiple chip holders are nested in the Z-direction, with lower potential chip holders positioned below higher potential chip holders. This nesting approach allows multiple potentials to coexist in a compact vertical arrangement, reducing the required package area while maintaining proper voltage isolation.
2Reliability
If the lead frame is divided into chip holders with different potentials, then high-voltage spacing is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent segments the package into multiple independent carriers, each carrier containing chip holders of specific potentials. This segmentation allows each carrier to be manufactured and prepared independently, then stacked together. The segmentation approach simplifies manufacturing by breaking down the complex multi-potential structure into manageable modular units that can be processed separately and assembled through stacking.
Solution Approach 2:
The patent resolves manufacturing complexity by moving from a complex planar routing problem to a vertical stacking problem. Instead of routing wires across a large planar lead frame with multiple potential zones, the solution stacks carriers vertically, allowing bonding wires to be routed within each carrier layer and then connected between layers through vertical interconnects. This dimensional change simplifies the routing process and reduces manufacturing difficulty.
3Adaptability or versatility
If the lead frame is divided into small chip holders, then different potentials are accommodated, but heat dissipation performance deteriorates
Solution Approach 1:
The patent maintains heat dissipation performance by utilizing vertical stacking to separate different potentials instead of dividing the lead frame into small horizontal segments. Each carrier can maintain a large thermal mass and efficient heat path to its respective heat sink, while vertical separation provides the necessary electrical isolation. This approach preserves the thermal performance of larger chip holders while achieving potential separation through the Z-direction.
4Reliability
If the lead frame is divided into chip holders with different potentials, then voltage isolation is achieved, but bonding wire routing difficulty increases
Solution Approach 1:
The patent dramatically reduces routing difficulty by transitioning from planar wire routing across multiple potential zones to vertical stacking with localized routing. Bonding wires are routed within each carrier layer where all chip holders are at similar potentials, eliminating the need to cross high-voltage boundaries in the horizontal plane. Vertical interconnects provide simple pathways between layers, reducing routing complexity compared to planar multi-potential arrangements.
Data Source
AI summary
A package structure includes a first carrier, a second carrier, and a first electronic device. The first carrier is electrically connected to a first voltage. The second carrier includes a first substrate and a first interconnect structure. The first substrate is in contact with the first carrier, the first interconnect structure is electrically connected to a second voltage, and the first interconnect structure and the first carrier are deposited on two opposite sides of the first substrate. The first electronic device is deposited on the first interconnect structure and away from the first carrier. The first electronic device is in contact with the first interconnect structure.