Semiconductor Package Power Distribution via Stacked Redistribution Layers
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Solution Overview
Problem
Conventional routing configurations for power and ground signals in semiconductor packages face challenges due to shrinking feature sizes, leading to increased manufacturing costs and inefficiencies in providing power to multiple semiconductor dies.
Innovation Solution
A semiconductor package design featuring a package substrate with multiple metal redistribution layers and electrical connectors that provide power to core logic components, allowing for efficient power distribution through input-power and output-power pads, and signal transmission via input/output pads, with a focus on reduced surface area and increased efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional routing configurations are used for power and ground signals, then manufacturing processes are simpler, but manufacturing cost increases and power distribution efficiency decreases
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical stacking with multiple redistribution layers (RDL0, RDL1, RDL2) at different heights. Power and ground signals are distributed through vertically stacked metal layers connected by vias, enabling three-dimensional power delivery that improves current density and reduces resistance compared to conventional flat routing.
Solution Approach 2:
The power distribution network is segmented into multiple functional layers: input power pads on the bottom surface, intermediate power/ground RDL layers in the middle, and output power pads on the top surface. This segmentation allows independent optimization of each layer's routing pattern and facilitates modular manufacturing processes.
2Adaptability or versatility
If feature sizes are shrunk to smaller dimensions, then device integration increases, but manufacturing cost and routing complexity increase
Solution Approach 1:
By stacking RDL layers vertically, the patent achieves higher integration density without proportionally increasing lateral routing complexity. The vertical dimension provides additional pathways for power and ground signals, reducing the need for complex lateral routing around shrinking feature sizes.
Solution Approach 2:
Different RDL layers are optimized for different functions: lower layers (RDL0) handle input power distribution with larger trace widths, while upper layers (RDL1, RDL2) handle output power and ground returns with optimized routing patterns. Each layer's geometry is locally optimized for its specific signal type and current requirements.
Data Source
AI summary
A semiconductor package includes a plurality of electrical connectors, a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads, and a plurality of input/output signal pads that carry signals to and from the core logic. Each pad of the semiconductor die has an electrical connector of the plurality of electrical connectors extending therefrom. The semiconductor package also includes a package substrate having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer. The first metal redistribution layer provides a first electrical potential to each of the input-power contact pads, and the second metal redistribution layer provides a second electrical potential to each of the output-power contact pads. Each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.