3D Semiconductor Package Layout for Power Noise Reduction
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Solution Overview
Problem
Current semiconductor packages face challenges in improving operation characteristics, such as reliability and size reduction, particularly in efficiently managing power delivery and noise reduction during high-frequency operations.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip with a logic structure and a second semiconductor chip with a power decoupling capacitor, where the first chip has a power delivery network connected through penetration vias, and the second chip's capacitor layer is adjacent to the power delivery network, enabling efficient power management and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor package structure is used with separate power delivery and logic components, then the package size is larger, but the operation characteristics and noise reduction are insufficient
Solution Approach 1:
The patent merges the power delivery network and logic structure onto a single semiconductor chip. The power delivery network includes power lines, ground lines, and decoupling capacitors that are integrated with the logic structure, eliminating the need for separate dedicated power management chips and reducing overall package size while improving operational efficiency and noise reduction.
Solution Approach 2:
The patent utilizes three-dimensional integration by placing the power delivery network on the back surface of the semiconductor chip while the logic structure remains on the front surface. Penetration vias connect the two surfaces, enabling vertical interconnection and allowing both power delivery and logic functions to coexist in the same chip footprint, thereby reducing package size without compromising functionality.
2Reliability
If power delivery network is integrated closer to logic structure, then noise is reduced and operation characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The power delivery network is segmented into distinct functional components: power lines for voltage delivery, ground lines for reference potential, and decoupling capacitors for noise filtering. Each component is strategically positioned and connected through penetration vias to the logic structure, allowing for modular manufacturing processes and simplified fabrication compared to a fully integrated monolithic design.
3Reliability
If decoupling capacitors are placed adjacent to power delivery network, then high-frequency noise is reduced, but chip area increases
Solution Approach 1:
The decoupling capacitors are nested within the power delivery network structure on the back surface of the chip. The capacitors are positioned in close proximity to the power lines and ground lines, effectively utilizing the available space within the power delivery network footprint. This nested arrangement provides high-frequency noise filtering without significantly increasing the overall chip area, as the capacitors share the same spatial envelope as the power delivery traces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the operation characteristics of semiconductor packages by effectively managing power delivery and reducing noise during high-frequency operations, thereby improving reliability and reducing size.
Implementation Method 1
penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure
Implementation Method 2
a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network
Data Source
AI summary
A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.