3D Semiconductor Package Layout for Stable Power and Reliability
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Solution Overview
Problem
As electronic devices become smaller and lighter, semiconductor packages face challenges in maintaining high performance and reliability while managing increasing power consumption, requiring improved structural reliability and efficient power supply solutions.
Innovation Solution
A semiconductor package design featuring a first and second redistribution structure, semiconductor chips, a bridge chip, and molding layers, with conductive posts and passive devices, to enhance electrical connections and stability, and a fabricating method that includes specific layer formations and bonding processes to reduce component size limitations and improve physical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor package size is reduced to make electronic devices smaller and lighter, then the portability improves, but the power consumption increases and structural reliability becomes more difficult to maintain
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and connected through conductive posts penetrating through intermediate layers, enabling compact packaging while maintaining adequate spacing and connection paths for power and signal distribution, thus preserving reliability in a reduced footprint.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically within a compact package body. The chips are arranged in layers with conductive posts and insulating layers nested between them, creating a space-efficient configuration that maximizes component density while maintaining structural integrity and power supply stability.
2Power
If more components are integrated to increase power consumption, then the performance and capacity improve, but the structural stability and power supply reliability become more challenging
Solution Approach 1:
The patent divides the power distribution system into multiple independent power supply layers, with each layer containing separate power lines and conductive posts. This segmentation allows independent power management for different chip stacks, isolating power supply fluctuations and failures to specific layers, thereby maintaining overall system stability even as total power consumption increases.
Solution Approach 2:
The patent implements localized power management by providing dedicated power supply paths and conductive posts for each semiconductor chip or chip group. Each region of the package has optimized local power distribution characteristics, allowing high-power components to receive adequate power while maintaining stability, and enabling differential power management strategies for different functional areas.
3Quantity of substance
If multiple semiconductor chips are integrated to increase capacity, then the functionality improves, but the manufacturing complexity and assembly difficulty increase
Solution Approach 1:
The patent employs preliminary bonding of conductive posts to the bottom surfaces of semiconductor chips before final package assembly. This pre-attachment step simplifies the subsequent stacking process, as chips with pre-bonded conductive posts can be directly positioned and connected to corresponding pads on intermediate layers, reducing the complexity of multi-chip integration and alignment operations.
Data Source
AI summary
Provided is a semiconductor package including a first redistribution structure, a second redistribution structure on the first redistribution structure, a plurality of semiconductor chips on an upper surface of the second redistribution structure, a bridge chip on a lower surface of the second redistribution structure, and a first molding layer between the first redistribution structure and the second redistribution structure and adjacent to the bridge chip, wherein the first molding layer is between the bridge chip and the first redistribution structure.