Semiconductor Package Backside Redistribution for Compact Power Routing
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Solution Overview
Problem
Existing semiconductor packages face challenges in providing efficient electrical connections between multiple transistor devices due to limited space, requiring innovative solutions for improved connectivity and space utilization.
Innovation Solution
The semiconductor package incorporates an auxiliary lateral redistribution structure on the rear surface of a semiconductor device, which is electrically insulated from the transistor device and provides flexible redistribution patterns, reducing the need for long connectors like bond wires and optimizing space usage by routing signals through a thick backside metallization layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional packaging methods with bond wires are used, then electrical connections can be established between devices, but the package space is insufficient and metal resistance is high
Solution Approach 1:
The patent utilizes the rear surface of the semiconductor device as an additional dimension for routing connections. By forming conductive patterns on the backside metallization layer, the invention creates a three-dimensional interconnection architecture that extends beyond the traditional planar two-dimensional layout, thereby increasing available routing space and reducing congestion in the package.
Solution Approach 2:
The rear surface metallization layer acts as an intermediary structure that facilitates electrical connections between devices. Instead of using long bond wires that traverse the entire package, the metallization layer provides a localized intermediate routing path that reduces connection length and resistance while improving spatial utilization.
2Reliability
If long connectors like bond wires are used, then electrical connections can be made between devices, but metal resistance increases and space is wasted
Solution Approach 1:
By routing connections through the rear surface metallization layer, the invention creates shorter, more direct electrical paths. This vertical integration approach reduces the horizontal distance that current must travel, thereby minimizing resistive losses and improving connection efficiency without sacrificing reliability.
3Quantity of substance
If more devices are placed in a single package, then power density increases, but connectivity between devices becomes more difficult
Solution Approach 1:
The invention segments the interconnection function into two distinct layers: the front surface for device mounting and the rear surface for routing. This segmentation allows each layer to be optimized independently, with the rear surface dedicated to creating organized, modular connection patterns that simplify the overall connectivity architecture even as device count increases.
Solution Approach 2:
The rear surface metallization provides an additional routing dimension that decouples device placement constraints from connection routing constraints. This allows devices to be densely packed on the front surface while connections are managed separately on the backside, reducing the complexity of inter-device connectivity.
Data Source
Figure 1a~1b
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AI summary
In an embodiment, a semiconductor package is provided that comprises at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device comprises a first transistor device having a source electrode, a gate electrode and a drain electrode, a front surface and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization comprises a first power contact pad coupled to the source electrode, the first power contact pad being mounted on the die pad. The rear metallization comprises a second power contact pad electrically coupled to the drain electrode and an auxiliary lateral redistribution structure that is electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.