Semiconductor Package Bonding Wire Layout for Stable Power Delivery
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Solution Overview
Problem
Semiconductor packages face power supply issues due to inductive reactance in longer wirings, leading to insufficient current delivery.
Innovation Solution
A semiconductor package design featuring a package substrate with multiple bonding wires connected in parallel between the chip and substrate pads, where power pads have larger cross-sectional area wires to minimize inductive reactance, while data signal pads use single wires to manage smaller current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If longer wirings are used to connect the chip to the package substrate, then the connection flexibility is improved, but the inductive reactance increases causing power supply issues
Solution Approach 1:
The patent divides the single long wiring connection into multiple shorter wiring segments connected in parallel. By segmenting the power delivery path into multiple shorter wires, the inductive reactance of each segment is reduced while maintaining the overall connection length and flexibility requirements.
Solution Approach 2:
The patent combines multiple wiring paths in parallel to achieve the desired connection. By merging multiple shorter wirings in parallel, the total current capacity is increased and the equivalent inductive reactance is reduced, resolving the power delivery stability issue while maintaining connection flexibility.
2Reliability
If multiple bonding wires are used in parallel for power connections, then the inductive reactance is reduced improving power delivery, but the device complexity increases
Solution Approach 1:
The patent applies different wiring configurations to different functional areas: power connections use multiple parallel wires to reduce inductive reactance, while signal connections use single wires to maintain simplicity. This localized differentiation resolves the contradiction by optimizing each connection type according to its specific requirements.
3Power
If larger cross-sectional area wires are used for power connections, then the current carrying capacity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
Instead of using a single large cross-sectional area wire that would be difficult to manufacture with high precision, the patent segments the current path into multiple smaller wires. The combined cross-sectional area of multiple smaller wires equals or exceeds that of a single large wire, achieving the same current carrying capacity while being more manufacturable with standard precision tolerances.
Data Source
AI summary
A semiconductor package includes a package substrate, a semiconductor chip and a plurality of bonding wires. The package substrate includes a connection pad. The semiconductor chip is disposed over the package substrate and includes a chip pad, a bonding pad, and a redistribution layer. The bonding pad is closer to a periphery of the semiconductor chip than the chip pad. The redistribution layer is connected between the chip pad and the bonding pad. The bonding wires are connected in parallel between the connection pad and the bonding pad.