Semiconductor Package Preparation Using Segmented Small Dies
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Solution Overview
Problem
Conventional semiconductor packages face limitations in miniaturization and cost reduction due to die sizes matching package sizes, leading to restricted die yield from wafers, high parasitic effects from high dielectric materials, and complex packaging processes involving metal wirings and multiple interfaces.
Innovation Solution
A method for preparing semiconductor packages by forming dies smaller than standard sizes, using conductive elements for electrical connection, and encapsulating with low dielectric constant materials via dry film processes, allowing for larger package sizes and reduced parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If die size is reduced to increase die yield from wafers, then manufacturing cost is reduced, but the package size becomes smaller than standard sizes
Solution Approach 1:
The patent divides the final package into multiple smaller dies that are formed on the wafer first, then encapsulated together. This segmentation allows each die to be small (improving yield) while the combined encapsulated package achieves standard size dimensions.
Solution Approach 2:
Multiple small dies are nested within a single encapsulation structure. The dies are arranged and encapsulated together to form a larger package that meets standard size requirements, similar to nested dolls where smaller objects are contained within a larger structure.
2Reliability
If high dielectric constant materials are used for encapsulation, then packaging protection is improved, but parasitic effects increase
Solution Approach 1:
The patent changes the dielectric constant parameter of the encapsulation material from high to low. By using low dielectric constant materials, the packaging still provides protection while significantly reducing parasitic capacitance and other harmful electromagnetic effects.
3Reliability
If metal wirings are used for electrical connection, then connectivity is achieved, but parasitic effects and process complexity increase
Solution Approach 1:
The patent extracts the metal wiring step from the packaging process. Instead of using separate metal wirings to connect dies to the substrate, the electrical connections are formed directly through conductive elements on the substrate during the encapsulation process, eliminating complex wire bonding operations.
4Ease of manufacture
If die size matches package size, then packaging simplicity is maintained, but die yield from wafers is restricted
Solution Approach 1:
The patent merges multiple small dies into a single encapsulated package unit. This combining approach maintains packaging simplicity (treating multiple dies as one unit) while allowing the individual dies to be smaller than standard sizes, thereby increasing the number of dies that can be produced from each wafer.
Data Source
AI summary
The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.