Semiconductor Package Warpage Mitigation via Localized Pressure

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Solution Overview

Problem

The existing fabrication methods of semiconductor packages face challenges with warpage of the encapsulant during the curing process, leading to misalignment of the Redistribution Layer (RDL) structure with semiconductor elements, which reduces product reliability and yield, especially as the carrier size increases.

Innovation Solution

A method involving a carrier with a pressure area around the semiconductor elements, where a pressure member is placed after carrier removal to support the encapsulant, maintaining structural flatness and enabling precise alignment of the RDL structure with the semiconductor elements, thereby improving reliability and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large carrier is used to support the encapsulant during curing, then the encapsulant can be properly cured, but warpage occurs on the edges of the encapsulant after carrier removal

Engineering Contradiction:
Improvecuring qualityVSAvoidflatness
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The patent applies preliminary action by defining a pressure area around the semiconductor element during encapsulant formation, and then applying pressure to this specific area after carrier removal. This pre-planned pressure application prevents warpage before it occurs, rather than trying to correct it afterward. The pressure area is prepared in advance during encapsulant formation, enabling targeted pressure application that maintains flatness without affecting the overall curing quality.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by concentrating pressure application to a specific pressure area surrounding the semiconductor element, rather than applying pressure uniformly across the entire encapsulant. This localized pressure approach addresses warpage at the edges where it occurs most severely, while maintaining the flatness of the central area where the semiconductor element is located. The pressure member is specifically positioned to apply force only to the problematic edge regions.

Inventive Principle:
Principle #3Local quality

2Productivity

If the carrier size is increased to support larger semiconductor elements, then more elements can be processed, but the position tolerance between semiconductor elements deteriorates

Engineering Contradiction:
Improveprocessing capacityVSAvoidposition tolerance
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by maintaining a consistent pressure area size around each semiconductor element regardless of the overall carrier size. This ensures that each element receives appropriate localized support and pressure, maintaining position tolerance and alignment precision. The pressure member is positioned to apply force only to the immediate vicinity of each semiconductor element, ensuring that elements remain properly aligned even when processed in large arrays on extended carriers.

Inventive Principle:
Principle #3Local quality

3Shape

If pressure is applied to the encapsulant after carrier removal, then warpage is reduced, but the structural integrity must be maintained

Engineering Contradiction:
ImproveflatnessVSAvoidstructural integrity
Core Design Contradiction:
ShapeVSStrength

Solution Approach 1:

The patent applies local quality by concentrating pressure application to a specific pressure area around the semiconductor element rather than applying pressure across the entire encapsulant surface. This localized approach reduces warpage in the critical edge regions while minimizing stress on the overall encapsulant structure. The pressure member is designed to apply force only where needed (at the edges and around the semiconductor element) without compromising the structural integrity of the central encapsulated region.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9337061B2Fabrication method of semiconductor package
Publication Date: 2016.05.10 SILICONWARE PRECISION IND CO LTD
  • US9337061B2 patent drawing
  • US9337061B2 patent drawing
  • US9337061B2 patent drawing

AI summary

A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.