Semiconductor Package Proximity Communication Design
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Solution Overview
Problem
Conventional semiconductor packages face issues with reduced thermal stability, increased thickness, and higher manufacturing costs due to the need for a dielectric layer between chips, which affects fine pitch and production efficiency.
Innovation Solution
A semiconductor package design featuring signal coupling pads and through-chip vias that allow for proximity communication between chips, reducing the need for a dielectric layer and enhancing thermal stability, with a method involving the precise spacing and electrical connection of pads and the formation of through-wafer vias for power and ground connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is disposed between the first chip and the second substrate, then the chips are electrically isolated, but the thermal stability is decreased, the thickness is increased and the manufacturing cost is increased
Solution Approach 1:
The patent removes the dielectric layer from between the first chip and second substrate, extracting the problematic insulating layer that caused thermal instability and increased thickness. Instead, direct bonding is used to achieve both electrical connection and thermal stability.
Solution Approach 2:
The patent merges the first chip and second substrate into direct contact through bonding, combining them into a unified structure that eliminates the need for intermediate dielectric layers, thereby improving thermal stability and reducing overall package thickness.
2Reliability
If a dielectric layer is disposed between the first chip and the second substrate, then the chips are electrically isolated, but the thickness of the semiconductor package is increased
Solution Approach 1:
The dielectric layer is extracted/removed from the structure, eliminating the source of increased thickness. Direct bonding between chips provides electrical isolation without requiring additional thickness from insulating materials.
Solution Approach 2:
By merging the chips through direct bonding, the overall package thickness is reduced as there is no need for the dielectric layer that would add to the total thickness of the assembly.
3Reliability
If a dielectric layer is disposed between the first chip and the second substrate, then the chips are electrically isolated, but the manufacturing cost is increased
Solution Approach 1:
The dielectric layer is extracted from the manufacturing process, eliminating the steps required to deposit, pattern, and etch the dielectric material, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
The direct bonding approach merges the chips in a single step that achieves both mechanical attachment and electrical connection, eliminating multiple processing steps that would be required with a dielectric layer, thus reducing manufacturing cost.
4Reliability
If a dielectric layer is disposed between the first chip and the second substrate, then the chips are electrically isolated, but the thermal stability of fine pitch is decreased
Solution Approach 1:
The dielectric layer is removed from the structure, eliminating the thermal interface that caused instability in fine pitch applications. Direct bonding provides superior thermal contact and stability for fine pitch features.
Solution Approach 2:
By merging the chips through direct bonding, thermal stability for fine pitch is improved as the direct contact eliminates thermal resistance and instability associated with dielectric layers, enabling more precise fine pitch manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves mass-production yield by controlling gap variations between signal coupling pads and enhancing thermal stability, thereby reducing manufacturing costs and increasing efficiency.
Implementation Method 1
The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip.
Data Source
AI summary
The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased.