Fan-Out Semiconductor Package Conductive Post Layout for Uniform RDL Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The bonding states between conductive pads and bumps, as well as copper posts and redistribution layers, in fan-out wafer-level packages (FOWLP) are critical for electrical connectivity but often face challenges in ensuring consistent and robust connections.
Innovation Solution
A semiconductor package design featuring conductive posts with varying dimensions and arrangements to ensure uniform electrical connection, where the posts have upper surfaces at the same height regardless of their distance from the semiconductor chip, enhancing the electrical connection between redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive posts are used to connect redistribution layers in FOWLP, then electrical connectivity is achieved, but bonding consistency and reliability become difficult to ensure
Solution Approach 1:
The patent applies parameter changes by varying the cross-sectional dimensions of conductive posts based on their distance from the semiconductor chip. Posts closer to the chip have smaller cross-sections while those farther away have larger cross-sections. This parameter adjustment compensates for bonding variations and ensures uniform bonding states across all posts, thereby improving electrical connection reliability without requiring enhanced manufacturing precision.
2Ease of manufacture
If uniform conductive posts are used for electrical connection, then manufacturing is simplified, but bonding state consistency varies with distance from the chip
Solution Approach 1:
The patent implements local quality by making each conductive post's cross-sectional dimensions specific to its location. Posts at different distances from the semiconductor chip have different cross-sectional areas, with closer posts being smaller and farther posts being larger. This localized differentiation ensures that each post achieves optimal bonding state consistency for its specific position, thereby improving overall bonding uniformity while maintaining manufacturing feasibility through systematic dimension variation.
Data Source
AI summary
A semiconductor package includes a first RDL containing a first redistribution wiring structure, a first semiconductor chip on the first RDL, a first mold on the first RDL and covering the first semiconductor chip, a second RDL on the first mold and containing a second redistribution wiring structure, a first conductive post extending through the first mold and contacting the first and second redistribution wiring structures and being spaced apart from the first semiconductor chip in a horizontal direction by a first distance, and a second conductive post extending through the first mold, contacting the first and second redistribution wiring structures and being spaced apart from the first semiconductor chip in the horizontal direction by a second distance greater than the first distance. A volume of the first conductive post is smaller than a volume of the second conductive post.