Semiconductor Package Structure Using RDL Bridge and Conductive Posts
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Solution Overview
Problem
Current semiconductor packaging technologies, such as the TSV process, face challenges with high complexity and cost, making it necessary to develop more efficient and cost-effective processes for stacking multiple memory chips within a single package while maintaining good electrical characteristics.
Innovation Solution
The proposed semiconductor package includes a first redistribution layer, a bridge chip attached to the redistribution layer, a mold layer enclosing the bridge chip, a second redistribution layer on top, conductive posts connecting the layers, and a first semiconductor chip mounted on the second redistribution layer, which enhances structural stability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a through-silicon via (TSV) process is used to stack multiple memory chips, then integration density is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The package substrate is divided into multiple redistribution layers (first and second RDLs) with distinct functional zones. The first RDL handles pad layer connections while the second RDL handles interconnection layer connections, separating the complexity of TSV routing into manageable segments that reduce overall process complexity
Solution Approach 2:
Conductive posts serve as intermediary elements that connect the first and second redistribution layers through the mold layer. These posts simplify the connection architecture by providing direct vertical interconnections between layers, eliminating the need for complex TSV routing while maintaining integration density
2Quantity of substance
If multiple chips are stacked in a single package, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The pad layer and interconnection layer are pre-formed on the package substrate before chip stacking. The first redistribution layer is prepared in advance with exposed pad regions, allowing subsequent chips to be aligned and connected to predetermined locations, thereby reducing alignment precision requirements during the stacking process
Solution Approach 2:
Different regions of the redistribution layer have different properties: the pad layer region has exposed conductive pads for direct chip connection, while the interconnection layer region has patterned conductors for signal routing. This local differentiation allows each region to be optimized for its specific function, simplifying the overall manufacturing process
3Manufacturing precision
If the pad layer surface is made flat, then manufacturing precision is improved, but structural stability decreases due to exposed pads
Solution Approach 1:
The substrate protection layer is selectively removed only in the pad layer region to expose the conductive pads, while being retained in the interconnection layer region to provide structural support and protection. This localized differentiation maintains surface flatness where needed while preserving structural stability where required
Data Source
AI summary
An example semiconductor package includes a first redistribution layer, a bridge chip attached to a top surface of the first redistribution layer, a mold layer on the first redistribution layer and enclosing the bridge chip, a second redistribution layer disposed on the mold layer, a conductive post extending through the mold layer vertically and connecting the first redistribution layer and the second redistribution layer, and a first semiconductor chip mounted on the second redistribution layer. The first redistribution layer includes a pad layer and an interconnection layer disposed on the pad layer. The pad layer includes a first insulating layer and pads in the first insulating layer. Top surfaces of the pads are exposed to an outside of a top surface of the first insulating layer, and bottom surfaces of the pads are exposed to an outside of a bottom surface of the first insulating layer.