Semiconductor Package RDL Integration Over Bonding Wire Structures
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Solution Overview
Problem
The existing fan out wafer level package manufacturing processes face difficulties in integrating semiconductor chips with bonding wiring structures due to incompatibility with redistribution wiring layers, making it challenging to perform redistribution wiring in wafer level.
Innovation Solution
The solution involves forming wiring bonding pads on a dummy substrate, stacking semiconductor chips, connecting them with bonding wires, and then forming a redistribution wiring layer on a mold substrate, which includes exposed wiring bonding pads to connect the redistribution wirings, allowing for the integration of chips with bonding wiring structures into the fan out wafer level package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a redistribution wiring layer is formed on a semiconductor chip with a bonding wiring structure, then the fan out wafer level package can be manufactured, but it is difficult to perform the redistribution wiring process in wafer level due to incompatibility
Solution Approach 1:
The patent introduces an intermediary layer structure between the bonding wiring and redistribution wiring. Specifically, a planarization layer is formed over the bonding wiring structure, and through-holes are created in this planarization layer to access the bonding pads. This intermediary structure enables the redistribution wiring process to be performed on chips with bonding wiring structures by providing a suitable interface for wire bonding or other interconnection methods.
Solution Approach 2:
The patent segments the interconnection structure into distinct functional layers: the bonding wiring layer for chip-to-substrate connection, the planarization layer for surface flattening and access, and the redistribution wiring layer for signal routing. This segmentation allows each layer to be optimized for its specific function and enables the redistribution wiring process to be performed separately from the bonding process.
2Reliability
If bonding wires are used to connect chip pads to the substrate, then the chip can be mounted, but the wiring bonding pads are hidden under the mold layer making redistribution wiring difficult
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement where bonding pads are on the chip surface to a three-dimensional structure where bonding pads are accessed through vertical through-holes in the mold layer. This dimensional change allows the bonding pads to remain connected to the chip while being accessible from the substrate side for redistribution wiring connection.
Solution Approach 2:
The patent performs preliminary actions by forming the planarization layer and through-holes in the mold layer before performing the redistribution wiring process. This preliminary preparation ensures that the bonding pads are accessible and properly positioned for subsequent wiring operations, making the redistribution process easier and more reliable.
Data Source
AI summary
A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.