Semiconductor Package Structure With Through-Hole RDL I/O Expansion
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Solution Overview
Problem
Package-on-package (PoP) semiconductor technology faces challenges in miniaturization due to large molding compound volume and limited I/O contacts, leading to increased manufacturing costs and size constraints.
Innovation Solution
The implementation of a semiconductor device structure that includes a substrate, a body structure with a semiconductor die, molding compound, conductive components, and redistribution layers (RDLs) to increase I/O contacts and reduce size through the use of through holes and multiple RDL layers for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If Package-on-package (PoP) structure is used to achieve high-density system integration, then the number of I/O contacts is reduced and size is minimized, but the volume of molding compound becomes excessively large
Solution Approach 1:
The patent transitions from a planar package layout to a three-dimensional stacked architecture with multiple redistribution layers (RDLs) at different heights. Through-holes penetrate the molding compound vertically, enabling electrical connections between stacked die structures. This vertical dimensionality change allows I/O contacts to be distributed across multiple layers, increasing total contact count without expanding the package footprint, while reducing the required molding compound volume compared to traditional PoP structures.
2Ease of manufacture
If traditional PoP structure is used, then manufacturing cost is reduced, but the number of I/O contacts is limited
Solution Approach 1:
The patent segments the electrical connection path into multiple independent redistribution layers (first RDL, second RDL, third RDL) distributed across different vertical levels. Each RDL provides additional routing paths and contact points, effectively multiplying the I/O capacity. The segmentation of connections across layers allows more signal paths to be packed into the same package volume, increasing I/O count without proportionally increasing manufacturing complexity or cost.
Solution Approach 2:
The patent implements a nested structure where smaller functional elements (conductive plugs, RDL traces, contact pads) are embedded within the molding compound matrix. Through-holes containing conductive plugs are nested within the molding compound, which itself is nested within the package housing. This nested arrangement allows multiple I/O contacts to be compacted into a limited space, increasing contact density while maintaining cost-effective manufacturing processes.
3Adaptability or versatility
If more I/O contacts are added to increase connectivity, then system integration performance is enhanced, but device size increases
Solution Approach 1:
The patent resolves the connectivity-size contradiction by exploiting the vertical dimension through stacked redistribution layers. Instead of horizontally spreading I/O contacts across a larger package area, the design stacks RDLs vertically at different heights, with through-holes providing inter-layer connections. This three-dimensional arrangement allows numerous I/O contacts to be accommodated within a compact footprint, enhancing connectivity without increasing device area.
Data Source
AI summary
A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.