Semiconductor Package Planarization Layer for RDL Short Prevention
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving enhanced electrical characteristics and structural stability while minimizing the likelihood of electrical shorts, particularly due to the formation of recesses in the molding layer that can cause shorts in the redistribution wiring structure.
Innovation Solution
A semiconductor package design that includes a molding layer with a high hardness and low coefficient of thermal expansion, featuring a recess at its upper surface, is combined with a planarization layer to create a void, preventing electrical shorts by forming redistribution layers on the flat surface of the planarization layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a molding layer with high hardness and low CTE is used, then structural stability is improved, but the likelihood of electrical shorts increases due to recess formation
Solution Approach 1:
A planarization layer is introduced as an intermediary between the molding layer and the second redistribution layer. This planarization layer has a flat upper surface that prevents electrical shorts while the lower surface conforms to the recessed upper surface of the molding layer, thus mediating between the structural stability requirement and the electrical short prevention requirement
2Reliability
If a planarization layer is added to prevent electrical shorts, then reliability is improved, but device complexity increases
Solution Approach 1:
The planarization layer serves multiple functions simultaneously: it provides a flat upper surface for the second redistribution layer to prevent electrical shorts, it conforms to the recessed molding layer surface through its lower surface, and it fills the void space between the molding layer and the redistribution layer, thus achieving multiple objectives with a single layer
Data Source
AI summary
A semiconductor package includes a first redistribution layer (RDL) including a first redistribution wiring structure, a first semiconductor chip on the first RDL and electrically connected to the first redistribution wiring structure, a molding layer on the first RDL and covering the first semiconductor chip and having one or more surfaces at least partially defining a recess at an upper surface of the molding layer, a planarization layer contacting the upper surface of the molding layer and having a flat upper surface, and a second redistribution layer (RDL) on the planarization layer and including a second redistribution wiring structure. The upper surface of the molding layer and a lower surface of the planarization layer collectively at least partially define a void between the upper surface of the molding layer and the lower surface of the planarization layer.