Semiconductor Package RDL Thickness Split for Logic-Power Integration
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Solution Overview
Problem
Existing semiconductor packages struggle to effectively integrate logic and power chips due to differing electrical and thermal requirements, with standard packages failing to provide optimal performance for both types of chips.
Innovation Solution
A semiconductor package design featuring two electrical redistribution layers of different thicknesses, where the first layer is thinner and optimized for logic chips with tight lines and connections, and the second layer is thicker for power chips requiring high current carrying and thermal management, using techniques such as subtractive structuring of metal sheets or leadframes for manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a standard uniform electrical redistribution layer is used for both logic and power chips, then the manufacturing process is simplified, but the electrical and thermal performance requirements of both chip types cannot be optimally met
Solution Approach 1:
The patent implements different thicknesses of electrical redistribution layers at different locations on the substrate. Specifically, a first electrical redistribution layer has a first thickness for logic chip connections, while a second electrical redistribution layer has a second thickness (greater than the first) for power chip connections. This local differentiation allows each region to be optimized for its specific electrical and thermal requirements without complicating the overall manufacturing process.
2Manufacturing precision
If thinner electrical redistribution layers are used for logic chips, then tight lines and connections are achieved, but high current carrying capability is insufficient
Solution Approach 1:
The patent creates locally optimized electrical redistribution layers with different thicknesses tailored to specific chip types. The first electrical redistribution layer with first thickness provides tight lines and precise connections for logic chips, while the second electrical redistribution layer with greater second thickness provides enhanced current carrying capability for power chips. Each layer's thickness is locally adapted to meet the specific requirements of the associated chip type.
Data Source
AI summary
A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.