Semiconductor Package Rear Through-Vias for Heat Dissipation
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Solution Overview
Problem
Semiconductor packages face challenges in achieving effective heat dissipation due to the low thermal conductivity of rear surface protective layers, which hampers the miniaturization and high-performance requirements of electronic devices.
Innovation Solution
The introduction of rear through-vias that penetrate through the rear protective layer and extend into the substrate, providing a vertical heat dissipation path, and the use of bump structures and adhesive layers to connect semiconductor chips, with the rear through-vias having a greater width than the front through-vias to enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rear surface protective layer is used to protect the substrate, then reliability is improved, but heat dissipation performance deteriorates due to low thermal conductivity
Solution Approach 1:
The protective layer is segmented by forming through-vias that divide the continuous protective layer into isolated regions. These through-vias create thermal pathways that penetrate the protective layer, allowing heat to escape from the substrate while the remaining protective layer material continues to provide mechanical protection. This segmentation resolves the contradiction by allowing both protection and heat dissipation to coexist.
Solution Approach 2:
The through-vias act as intermediary structures that bridge the protective layer and the substrate. They provide a thermal conduit that allows heat to transfer from the substrate through the protective layer to the external environment, while the protective layer material surrounding the via maintains its protective function. This intermediary structure enables simultaneous achievement of protection and heat dissipation.
2Temperature
If rear through-vias are made wider to enhance heat dissipation, then heat dissipation performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies that rear through-vias have a width greater than front through-vias, optimizing the thermal conductivity parameter for heat dissipation. By carefully controlling this parameter difference within manufacturing capabilities, the patent achieves improved heat dissipation while maintaining manufacturability. The parameter change is designed to balance thermal performance with fabrication feasibility.
3Temperature
If multiple through-vias are formed to improve heat dissipation, then heat dissipation performance is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the through-via structure: electrical connection function and thermal dissipation function. The same through-vias that provide electrical connectivity between layers also serve as heat dissipation pathways. This merging of functions reduces overall device complexity compared to having separate dedicated thermal pathways, as the existing electrical interconnect structure is dual-utilized for thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves heat dissipation characteristics by creating an effective thermal path and securing reliable electrical connections between chips, thereby addressing the thermal management issues in semiconductor packages.
Implementation Method 1
a plurality of rear through-vias penetrating through the rear protective layer and extending into the substrate
Implementation Method 2
a plurality of bump structures between the plurality of rear pads of the first semiconductor chip and the plurality of front pads of the second semiconductor chip
Implementation Method 3
an adhesive layer surrounding the plurality of bump structures between the first semiconductor chip and the second semiconductor chip
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a substrate having a front surface and an opposite rear surface, a rear protective layer on the rear surface, a plurality of first and second rear through-vias penetrating through the rear protective layer and extending into the substrate, a plurality of front through-vias extending from the front surface and connected to the first rear through-vias, and a plurality of rear pads on the rear protective layer and connected to the plurality of first and second rear through-vias. A second semiconductor chip is on the first semiconductor chip, and includes a plurality of front pads electrically connected to the plurality of rear pads by respective bump structures. Each of the plurality of rear through-vias has a width greater than a width of each of the plurality of front through-vias.