Semiconductor Package Recess Structure for Thinner Interconnect Assembly
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Solution Overview
Problem
The integration of larger electronic components into semiconductor device packages increases the package's area and thickness, hindering miniaturization due to the need for covering these components, which wastes space and complicates electrical connections.
Innovation Solution
A semiconductor device package design featuring a substrate with an interconnection structure and a package body that partially covers the interconnection structure, with a recess exposing a portion of the interconnection structure's lateral surface to enhance electrical connectivity and reduce package thickness, using a method that includes forming a recess on the package body to expose the interconnection structure, thereby increasing the contact area and providing a position limiting structure for components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a package body fully covers the interconnection structure to protect it, then reliability is improved, but the package thickness increases and miniaturization is hindered
Solution Approach 1:
The package body is segmented into different regions: a first region that covers the interconnection structure for protection, and a second region with a recess that exposes part of the interconnection structure. This segmentation allows selective coverage, protecting vulnerable areas while exposing areas needed for electrical connection, thereby reducing overall package thickness without compromising reliability.
Solution Approach 2:
Different regions of the package body have different coverage qualities. The first region provides full coverage for protection, while the second region provides partial coverage to expose the interconnection structure. This local differentiation in coverage quality allows the package to simultaneously achieve protection and miniaturization by applying coverage only where necessary.
2Length of stationary object
If the package body partially covers the interconnection structure to reduce thickness, then miniaturization is enabled, but electrical connection reliability may be compromised
Solution Approach 1:
The package body is divided into coverage and non-coverage regions, allowing electrical connections to be established in the exposed region while maintaining protection in the covered region. This segmentation enables reliable electrical connection without requiring full coverage, thus achieving miniaturization.
Solution Approach 2:
The recess in the package body creates a vertical dimension variation, exposing the lateral surface of the interconnection structure. This dimensional change provides additional contact area for electrical connections, ensuring reliability while reducing overall package thickness.
3Adaptability or versatility
If larger electronic components are integrated into the package, then functionality is improved, but the package area and thickness increase
Solution Approach 1:
The recess structure utilizes vertical space by exposing the lateral surface of the interconnection structure, allowing electrical connections to be made in the vertical dimension rather than requiring additional horizontal area. This enables larger components to be integrated without proportionally increasing package area.
Solution Approach 2:
The package body with its recess structure allows the interconnection structure to be partially nested within the package body and partially exposed. This nesting arrangement optimizes space utilization, allowing larger components to be accommodated without excessive increase in package area.
Data Source
AI summary
The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, an interconnection structure, a package body, and a first electronic component. The interconnection structure is disposed on the substrate. The package body is disposed on the substrate and partially covers the interconnection structure. The package body has a position limiting structure around the interconnection structure. The first electronic component is disposed on the interconnection structure and electrically connected to the interconnection structure.