Semiconductor Package Recess Filling for Delamination Resistance
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Solution Overview
Problem
Semiconductor packages face challenges in achieving high structural reliability due to the need for compactness, lightness, and high performance, which is compromised by recesses formed during planarization that can lead to delamination and filler loss, affecting the package's structural integrity.
Innovation Solution
A semiconductor package design that includes a first redistribution structure with a molding layer having recesses, filled by a gap-fill insulating layer, and a second redistribution structure with a photo-imageable dielectric lower redistribution insulating layer, enhancing structural reliability by filling these recesses and maintaining electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If planarization is performed on the molding layer to achieve a flat surface, then surface flatness is improved, but recesses are formed that lead to delamination and filler loss, worsening structural reliability
Solution Approach 1:
The patent applies preliminary action by forming the gap-fill insulating layer before subsequent processing steps. This layer is deposited in advance to fill the recesses that will be created during planarization, preventing delamination and filler loss before they can occur. The gap-fill layer is formed on the molding layer prior to any planarization operation, ensuring that when the surface is flattened, the recesses are already filled and structurally sound.
2Weight of moving object
If the molding layer is made compact and thin to reduce package size and weight, then package compactness and lightness are improved, but structural reliability deteriorates due to increased susceptibility to delamination
Solution Approach 1:
The patent employs composite materials by introducing a gap-fill insulating layer with different material properties than the molding layer. This composite structure combines the lightweight benefits of a thin molding layer with the structural reinforcement provided by the gap-fill layer, which has superior adhesion and mechanical properties. The composite design allows the package to remain compact and light while the additional layer prevents delamination and enhances overall structural reliability.
3Reliability
If recesses are filled to prevent delamination and improve reliability, then structural reliability is improved, but device complexity increases due to additional layers and processes
Solution Approach 1:
The gap-fill insulating layer serves multiple functions simultaneously: it fills the recesses to prevent delamination, provides electrical insulation, and acts as an adhesive barrier layer. By designing this single layer to perform multiple functions, the patent improves structural reliability without proportionally increasing device complexity. The multi-functionality of the gap-fill layer means that one additional layer addresses multiple potential failure modes rather than requiring separate structures for each function.
Data Source
AI summary
A semiconductor package includes a first redistribution structure, a first semiconductor chip on the first redistribution structure, a first molding layer on the first redistribution structure, the first molding layer including at least one lower recess in a top surface thereof and being disposed on the first semiconductor chip, connection structures on the first redistribution structure, the connection structures extending in a vertical direction and passing through the first molding layer, a first insulating layer on the first molding layer, and a second redistribution structure including a lower redistribution insulating layer on the first insulating layer, wherein the first insulating layer at least partially fills the at least one lower recess of the first molding layer.