Semiconductor Package Recess Layout for Adhesive Overflow Control
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Solution Overview
Problem
The warpage of substrates during the fabrication of semiconductor packages can lead to defects due to the excessive protrusion of adhesive layers, causing non-wet defects and contact defects between the interposer and package substrate.
Innovation Solution
A semiconductor package design featuring a buffer die with a passivation layer and recesses formed on its surface to prevent adhesive layer overflow, combined with a method of thermal compression bonding core chips onto the buffer die, where the recesses are strategically positioned to prevent adhesive layer overflow and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thermal compression bonding is performed to bond the semiconductor chip to the substrate, then bonding strength is improved, but adhesive layer overflow occurs causing warpage defects
Solution Approach 1:
The patent applies a non-conductive film (adhesive layer) to the semiconductor chip before bonding, and pre-forms protrusions on the substrate surface at designated bonding positions. This preliminary preparation ensures that during thermal compression bonding, the adhesive layer is confined to these protrusion regions, preventing overflow while maintaining bonding strength.
Solution Approach 2:
The substrate surface is designed with localized protrusions at specific bonding positions rather than a uniform surface. This creates different surface characteristics in different locations - raised areas for precise adhesive confinement and flat areas elsewhere. The protrusions serve as physical barriers that locally contain the adhesive layer during bonding, preventing warpage defects.
2Area of stationary object
If the adhesive layer protrudes beyond the chip edge to form a filet, then bonding coverage is improved, but substrate warpage occurs causing defects
Solution Approach 1:
The substrate is pre-formed with protrusions at the exact locations where bonding is needed, before the bonding process begins. This preliminary structuring of the substrate ensures that when adhesive is applied and compressed, it naturally confines to these protrusion areas, achieving adequate bonding coverage without excessive protrusion that would cause warpage.
Solution Approach 2:
The substrate surface features localized protrusions that create distinct bonding zones. These protrusions provide just enough surface area for reliable bonding while physically limiting adhesive spread. The raised structures ensure bonding coverage is concentrated where needed without causing the adhesive to overflow into areas that would induce substrate warpage.
3Reliability
If thermal compression bonding pressure is increased to improve bonding quality, then bonding reliability is improved, but adhesive layer deformation increases causing overflow
Solution Approach 1:
The substrate protrusions are formed in advance to serve as physical boundaries for the adhesive layer. During thermal compression bonding, these pre-formed protrusions act as molds that contain the adhesive, allowing higher bonding pressures to be applied without causing uncontrolled adhesive deformation or overflow. The protrusions maintain adhesive shape while enabling reliable bonding.
Solution Approach 2:
The protrusions create localized bonding zones with confined geometry. Within these confined spaces, high compression pressure can be effectively applied to ensure reliable bonding between the chip and substrate, while the protrusion walls prevent the adhesive from deforming outward. This local confinement allows high pressure bonding without the harmful shape changes that would occur on a flat surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the formation of filets and minimizes defects such as non-wet and contact defects, enhancing the reliability and performance of semiconductor packages by preventing adhesive layer overflow and ensuring proper bonding.
Implementation Method 1
stacking the core chip on the buffer die by performing thermal compression bonding between the buffer die and the core chip
Data Source
AI summary
Semiconductor package and fabricating method thereof are provided. Semiconductor package comprises a buffer die including a semiconductor substrate having a first surface and a second surface, which face each other, and a passivation layer formed on the first surface, a plurality of core chips stacked on the buffer die, including a first core chip, which is disposed at a lowermost end, among the plurality of core chips, an adhesive layer between the buffer die and the first core chip, and a mold layer surrounding an upper surface of the buffer die and the plurality of core chips, wherein a plurality of recesses recessed inward from an upper surface of the passivation layer are formed on the upper surface of the passivation layer, and the plurality of recesses are formed to surround the first core chip and do not overlap the first core chip horizontally.