Semiconductor Package Recess Layout for Mold-Bond Reliability
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Solution Overview
Problem
The reliability of semiconductor packages is compromised due to differences in physical properties between the non-conductive material exposed on the side surfaces of semiconductor chips and the mold layer, leading to potential failures.
Innovation Solution
Incorporating a non-conductive material layer with recess areas that extend in one direction and are spaced apart in another direction, featuring voids or empty spaces, to improve bonding and protect the semiconductor chips and substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-conductive material is applied to bond substrate and semiconductor chips, then bonding between substrate and chips is achieved, but exposed non-conductive material on side surfaces creates reliability issues due to physical property differences with mold layer
Solution Approach 1:
The patent removes the harmful exposed non-conductive material from the side surfaces of semiconductor chips through recess formation. By extracting the problematic material that causes physical property mismatch, the reliability issue is resolved while maintaining the bonding function of the non-conductive material layer underneath.
Solution Approach 2:
The patent applies different treatments to different regions: the non-conductive material is retained in the bonding area between substrate and chips, but removed from the side surface exposure areas. This local differentiation ensures bonding functionality is preserved while eliminating the reliability hazard from exposed material.
2Area of stationary object
If non-conductive material layer is formed completely covering the substrate, then bonding coverage is maximized, but exposed material on chip side surfaces reduces reliability
Solution Approach 1:
The non-conductive material layer is segmented into two functional zones: a bonding zone that maintains full coverage between substrate and chips, and side surface zones where material is recessed or removed. This segmentation preserves bonding coverage while eliminating exposed material that compromises reliability.
Solution Approach 2:
Different regions of the non-conductive material layer have different configurations: complete coverage in the bonding area versus recessed or removed material at side surfaces. This local quality differentiation resolves the contradiction between maintaining bonding coverage and preventing reliability issues from exposure.
3Ease of manufacture
If conventional bonding process is used, then manufacturing simplicity is maintained, but exposed non-conductive material creates potential failures
Solution Approach 1:
The recess formation is performed as a preliminary action before mold layer application. By pre-removing the exposed non-conductive material, the subsequent molding process avoids the reliability issue without requiring complex modifications to the bonding process itself, thus maintaining manufacturing simplicity while improving reliability.
Solution Approach 2:
The recess formation process acts as an intermediary step between bonding and molding. This intermediate treatment eliminates the harmful exposed material, serving as a bridge that connects the simple bonding process with the reliability requirements of the final package structure.
Data Source
AI summary
A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes: a substrate extending in first and second directions intersecting each other; a non-conductive material layer on the substrate; and a semiconductor chip on the non-conductive material layer, wherein the non-conductive material layer includes a plurality of first recess areas, wherein each of the plurality of first recess areas extends in the first direction and inwardly of a side surface of the semiconductor chip, wherein the plurality of first recess areas are spaced apart from each other in the second direction, wherein at least one of the plurality of first recess areas defines a void.