Semiconductor Package Structure with Recessed Cavity for Lead Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional quad flat non-leaded (QFN) semiconductor package manufacturing methods face issues with molding compound overflow due to direct contact between leadframe leads and the molding compound, affecting electrical reliability and increasing manufacturing costs, especially since the distance between leads cannot be minimized effectively.

Innovation Solution

A semiconductor package structure and manufacturing method that utilize a supporting plate and padding patterns to form leads extending from the top surfaces along side surfaces into a containing cavity, where a chip is mounted and encapsulated with molding compound, exposing only a portion of the leads, and the supporting plate is removed after molding compound formation to prevent overflow and allow for finer pitch lead formation using electroplating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the leads of the leadframe contact the molding compound directly and are co-planar with it, then the manufacturing process is simple, but the molding compound overflows to the lower surface of leads affecting electrical reliability

Engineering Contradiction:
Improveelectrical reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary structure (support plate with recessed cavity) between the leads and the molding compound. The leads are positioned within the recessed cavity formed by the support plate and padding patterns, preventing direct contact with the molding compound surface. This intermediary structure controls the positioning of leads and prevents molding compound overflow while maintaining electrical reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the distance between leads is not minimized, then the package structure is simple, but an extra redistribution layer (RDL) has to be created increasing manufacturing cost

Engineering Contradiction:
Improvemanufacturing costVSAvoiddistance between leads
Core Design Contradiction:
Ease of manufactureVSLength of moving object

Solution Approach 1:

The patent utilizes the vertical dimension by forming leads that extend downward into the recessed cavity of the support plate. This vertical arrangement allows leads to be positioned closer together horizontally without interfering with each other, eliminating the need for additional redistribution layers and reducing manufacturing costs while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If the leads are formed with finer pitch for miniaturization, then the application range increases, but the manufacturing precision requirement increases

Engineering Contradiction:
Improveapplication rangeVSAvoidlead formation precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The support plate with pre-formed recessed cavity and padding patterns provides a predetermined structure that guides lead formation. This preliminary structure ensures that leads are automatically positioned at the correct locations with proper spacing, enabling finer pitch leads to be formed with consistent precision and facilitating miniaturization for various applications.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method prevents molding compound overflow, enhances electrical reliability, reduces manufacturing costs, and supports miniaturization by allowing for finer pitch leads and increased application range through exposed lead portions suitable for external connections.

Implementation Method 1

a molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill gaps among the containing cavity and the padding patterns, and expose a portion of the leads located on the top surfaces of the padding patterns

Methodology Applied
Scientific EffectEncapsulation:

Implementation Method 2

The supporting plate is removed to expose a back surface opposite to the top surface of each of the padding patterns, a bottom surface of the molding compound, and a lower surface of each of the leads

Methodology Applied
Scientific EffectMaterial removal:

Data Source

PatentUS9053968B2Semiconductor package structure and manufacturing method thereof
Publication Date: 2015.06.09 CHIPMOS TECH INC
  • US9053968B2 patent drawing
  • US9053968B2 patent drawing
  • US9053968B2 patent drawing

AI summary

A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.