Semiconductor Package Recessed Chip Stacking
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high performance, compact size, efficient heat radiation, and structural stability, especially when multiple semiconductor chips are packaged together, as they often result in increased size and reduced electrical connectivity.
Innovation Solution
A semiconductor package design that incorporates a first substrate with a recessed area for a semiconductor chip, an interposer substrate with an adhesive layer, and a molding layer, which enhances electrical connectivity and structural stability while allowing for efficient heat dissipation through the use of thermal conductive members in the adhesive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted in a single package, then electrical connectivity and functionality are improved, but package size increases
Solution Approach 1:
The patent implements package-on-package stacking where a first semiconductor chip is mounted on a first substrate, and a second semiconductor chip is mounted on a second substrate that is stacked above the first substrate. The substrates are nested vertically, allowing multiple chips to be integrated in a compact three-dimensional configuration rather than spreading them out horizontally, thus improving electrical connectivity while minimizing package size expansion.
Solution Approach 2:
The patent transitions from a planar two-dimensional chip arrangement to a three-dimensional vertical stacking configuration. By utilizing the vertical dimension (Z-axis) for mounting multiple substrates at different heights, the design achieves enhanced electrical connectivity and functionality without proportionally increasing the horizontal footprint of the package.
2Volume of moving object
If compact packaging is implemented, then package size is reduced, but heat radiation efficiency deteriorates
Solution Approach 1:
The patent introduces a molding layer as an intermediary substance filled between the stacked substrates and chips. This molding layer serves multiple functions: it provides mechanical support and structural stability for the compact stacked configuration, while simultaneously enabling efficient heat radiation pathways. The molding material acts as a thermal conduit that facilitates heat dissipation from the densely packed chips, resolving the conflict between compact size and heat radiation efficiency.
3Adaptability or versatility
If complex multi-layer structure is used, then electrical connectivity is improved, but structural stability deteriorates
Solution Approach 1:
The patent merges the first substrate and second substrate into a unified stacked structure, with the molding layer filling the space between them. This integration creates a single stable composite structure where the substrates, chips, and molding layer work together as one cohesive unit. The molding layer bonds the substrates together, providing mechanical reinforcement that maintains structural stability despite the complexity of the multi-layer electrical interconnection architecture.
Solution Approach 2:
The patent uses a molding layer that provides uniform mechanical and thermal properties throughout the package structure. This homogeneous material fills the irregular spaces between stacked substrates and chips, creating consistent structural support and thermal pathways. The uniformity of the molding layer ensures balanced stress distribution and stable thermal management across the entire multi-layer assembly, maintaining structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved electrical characteristics, enhanced structural stability, and efficient heat radiation, resulting in a compact and high-performance semiconductor package.
Implementation Method 1
efficient heat radiation through the use of thermal conductive members in the adhesive layer
Data Source
AI summary
A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate.