Semiconductor Package Recessed Substrate for Height Reduction
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Solution Overview
Problem
Semiconductor packages face challenges in achieving a thin and lightweight design while maintaining structural reliability, particularly due to the height of semiconductor chips and adhesion issues between chips and adhesion layers.
Innovation Solution
A semiconductor package design featuring a package substrate with a recessed region, where semiconductor chips are positioned within this recessed area, reducing the overall height and improving adhesion through specific layer configurations and bonding methods, such as flip-chip and wire bonding, to enhance structural reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked on the package substrate to increase storage capacity, then the storage capacity increases, but the package height increases
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking of semiconductor chips, utilizing the third dimension (height) to increase storage capacity. Multiple chips are stacked in the vertical direction above the package substrate, transforming the spatial arrangement from two-dimensional to three-dimensional configuration.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically, with each chip positioned above the previous one. The interlayer insulating layers are nested between the chips, creating a compact vertical arrangement that maximizes space utilization while maintaining structural integrity.
2Length of stationary object
If semiconductor chips are made thinner to reduce package height, then the package height decreases, but the adhesion between chips and adhesion layers deteriorates
Solution Approach 1:
The patent applies different material properties to different regions of the adhesion layers. The adhesion layers are configured with specific material compositions and thickness variations in different areas to optimize both the thin profile requirement and the adhesion strength. This local differentiation of material quality allows simultaneous achievement of reduced height and maintained adhesion.
Solution Approach 2:
The patent employs composite material structures for the adhesion layers, combining multiple materials with complementary properties. The adhesion layers may include combinations of organic and inorganic materials, or materials with different mechanical and adhesive properties, to achieve both thin dimensions and strong adhesion to the semiconductor chips.
3Reliability
If wire bonding is used to connect chips to the package substrate, then electrical connection is achieved, but the package size increases
Solution Approach 1:
The patent utilizes vertical vias to establish electrical connections between the stacked chips and the package substrate, transitioning from horizontal wire bonding to vertical connection paths. The vias penetrate through the interlayer insulating layers in the vertical direction, enabling compact electrical interconnection that reduces package footprint while maintaining reliable electrical connectivity.
Data Source
AI summary
A semiconductor package includes a package substrate including an insulating layer having an upper surface and a lower surface and provided with a first region which is recessed to a first depth from the upper surface toward the lower surface, a redistribution wiring buried in the insulating layer, a chip connection pad on a bottom surface of the recessed first region and connected to the redistribution wiring, and a wire connection pad on the upper surface of the insulating layer and connected to the redistribution wiring, a first semiconductor chip overlapping, in a top-down view of the semiconductor package, the recessed first region of the insulating layer and comprising a first chip pad connected to the chip connection pad of the package substrate, and a second semiconductor chip on the first semiconductor chip and connected to the wire connection pad of the package substrate through a conductive wire.