Semiconductor Package With Recessed Substrate For Thickness Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packaging methods result in increased package thickness, longer wiring paths, and higher electric resistance, which hinder the development of high-speed, compact electronic components with stable bonding.
Innovation Solution
A semiconductor package design featuring a base substrate with a recessed portion on one surface, where a first semiconductor chip is mounted on the opposite surface, and a second semiconductor chip with a through via is inserted into the recessed portion, connected to a connection pad, and a protection layer fills the gap, reducing overall thickness and enhancing bonding stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are laminated and mounted on one substrate, then the functionality and integration are improved, but the package thickness increases
Solution Approach 1:
The patent implements nesting by placing the second semiconductor chip inside a recessed portion formed in the first semiconductor chip. This allows one chip to be embedded within another, reducing the overall vertical height of the package while maintaining the functionality of both chips. The recessed portion is specifically designed to accommodate the second chip, enabling a nested configuration that solves the thickness problem.
Solution Approach 2:
The patent transitions from a planar arrangement where chips are stacked vertically to a three-dimensional arrangement utilizing a recessed portion. By creating a cavity in the first chip and embedding the second chip within it, the design uses vertical space more efficiently, reducing the overall package thickness while maintaining chip functionality.
2Productivity
If multiple packages are laminated together, then the integration density is improved, but the wiring path length increases and electric resistance increases
Solution Approach 1:
By nesting the second chip within the first chip's recessed portion, the patent minimizes the vertical distance between corresponding pads and connection points. This reduces the length of bonding wires or interconnects needed to establish electrical connections, thereby reducing overall wiring path length and associated resistance.
3Length of stationary object
If the package thickness is reduced by inserting chips into recessed portions, then the package size is improved, but the bonding stability may deteriorate
Solution Approach 1:
The patent applies beforehand cushioning by filling the gap between the second chip and the recessed portion with a protective layer. This layer compensates for any dimensional variations or stress concentrations that might occur due to the nested configuration, ensuring stable bonding and reliable electrical connections while maintaining the reduced thickness.
Solution Approach 2:
The patent uses a composite structure consisting of the semiconductor chips, the recessed portion, and the protective layer material. This composite approach combines different materials with complementary properties to achieve both reduced thickness and maintained bonding stability, as the protective layer provides mechanical support and stress distribution.
Data Source
AI summary
A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second chip in the recessed portion, the second semiconductor chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second semiconductor chip in the recessed portion, the second chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via.