Semiconductor Package With Recessed Substrate For Compact Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor package-on-package (PoP) structures face challenges in achieving a fine pitch for connecting elements and maximizing wire bonding area due to their thickness and design limitations, which hinders the development of high-performance, compact electronic systems.
Innovation Solution
The proposed semiconductor package design includes a first package with a lower semiconductor chip mounted on a substrate and a second package stacked on top, featuring a chip region with recessed and protruding surfaces, allowing upper semiconductor chips to be mounted on opposite edges and connected via bonding wires, with connecting elements between the packages to reduce thickness and increase wire bonding area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional PoP structure is used with each package having a semiconductor chip and package substrate, then the package can be stacked to increase integration, but the thickness becomes large which is undesirable
Solution Approach 1:
The lower semiconductor chip is inserted into a recess region formed in the second package substrate, creating a nested configuration where one component fits within the structure of another. This nesting approach reduces the overall thickness of the stacked package while maintaining the integration of multiple chips and substrates.
Solution Approach 2:
The invention transitions from a conventional planar stacking approach to a three-dimensional configuration with recessed and protruding portions. By forming a recess region in the second package substrate and inserting the lower chip into it, the design utilizes vertical dimensionality to reduce thickness while preserving horizontal integration.
2Length of stationary object
If the package structure is optimized for compactness, then thickness is reduced, but the area for wire bonding becomes limited
Solution Approach 1:
The second package substrate is segmented into distinct functional regions: a chip region with recessed and protruding portions for mechanical integration, and a connection region with extended bonding pads for wire bonding. This segmentation allows the wire bonding area to be spatially separated and optimized independently from the chip mounting area, enabling sufficient bonding area even in a compact thickness profile.
Solution Approach 2:
Different regions of the second package substrate are given different local qualities: the chip region has recessed and protruding features for mechanical interlocking, while the connection region has extended bonding pads specifically optimized for wire bonding. This local differentiation allows each region to perform its function optimally without compromising the other.
3Length of stationary object
If connecting elements are placed between packages to reduce thickness, then the pitch of connecting elements must be minimized, but this increases manufacturing difficulty
Solution Approach 1:
The connecting elements are arranged in a three-dimensional configuration that utilizes the vertical space created by the recessed structure. By forming vias and conductive paths through the recessed portion of the second package substrate, the design achieves fine effective pitch without requiring excessively dense surface mounting, thereby reducing manufacturing difficulty while maintaining compact thickness.
Data Source
AI summary
Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.