Semiconductor Package Recessed Terminal Layout for Warpage Stability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved structural stability and increased productivity, particularly in the spacing and connection of semiconductor chips and substrates, which affects their reliability and durability.
Innovation Solution
A semiconductor package design featuring a first substrate with a semiconductor chip and a molding layer having recesses, where substrate connection terminals are positioned in these recesses to electrically connect a second semiconductor package, enhancing structural stability and allowing for horizontal spacing between chips, and a method of fabrication involving the formation of preliminary connection terminals, molding layers, and testing before assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are mounted closely on the substrate to increase integration density, then productivity and area utilization are improved, but structural stability deteriorates due to warpage and connection reliability issues
Solution Approach 1:
The substrate surface is segmented into multiple regions with recesses that physically separate connection terminals from each other and from semiconductor chips. This segmentation allows chips to be mounted closely together while maintaining structural stability through the distributed support provided by recesses throughout the substrate surface.
Solution Approach 2:
The connection terminals are moved from a two-dimensional planar arrangement to a three-dimensional configuration by placing them in recesses that extend downward from the substrate surface. This vertical dimensionality change allows terminals to be positioned below the chip mounting plane, enabling close chip spacing without compromising connection reliability or structural stability.
2Area of stationary object
If connection terminals are positioned close to semiconductor chips for compact design, then area utilization is improved, but manufacturing precision deteriorates due to alignment difficulties and connection reliability issues
Solution Approach 1:
Connection terminals are positioned in recesses below the chip mounting plane, creating a vertical separation between chips and terminals. This three-dimensional arrangement maintains compact horizontal footprint while significantly improving alignment precision, as chips can be accurately positioned on the substrate surface without the need for precise lateral alignment with terminals located in subsurface recesses.
Solution Approach 2:
The recesses act as intermediary structures that mediate between the chip mounting surface and the connection terminals. By providing a dedicated subsurface location for terminals, the recesses simplify the manufacturing process and improve alignment precision without requiring complex lateral positioning arrangements.
3Reliability
If a thick molding layer is used to cover all connection terminals for protection, then reliability is improved, but productivity deteriorates due to increased material usage and longer curing time
Solution Approach 1:
Connection terminals are extracted from the planar substrate surface and positioned in recesses below the chip mounting plane. This extraction eliminates the need for a thick molding layer to cover protruding terminals, as the recesses themselves provide protection. Consequently, a thinner molding layer suffices for encapsulation, reducing material usage and curing time while maintaining connection protection and reliability.
4Ease of operation
If all connection terminals are exposed on the substrate surface for easy connection, then ease of operation is improved, but structural stability deteriorates due to substrate warpage
Solution Approach 1:
Connection terminals are repositioned from the two-dimensional substrate surface to a three-dimensional configuration within recesses. This vertical relocation maintains connection accessibility through the recess openings while distributing mechanical stresses more evenly throughout the substrate structure, thereby preventing warpage and maintaining substrate flatness.
Solution Approach 2:
The substrate structure is made non-uniform by creating localized recesses at specific connection terminal positions. This local modification allows terminals to be accessible for connection while the surrounding substrate maintains its structural integrity and flatness. The recesses are strategically positioned to provide connection access without compromising overall substrate stability.
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate, a first semiconductor chip on the first substrate, a molding layer on the first substrate and the first semiconductor chip and has a plurality of recesses, a plurality of substrate connection terminals on the first substrate and in the plurality of recesses, and a second semiconductor chip on the plurality of substrate connection terminals. The plurality of recesses and the plurality of substrate connection terminals are horizontally spaced apart from the first semiconductor chip. The molding layer is spaced apart from the second semiconductor chip.