Semiconductor Package Redistribution Circuit Non-Planar Metallization
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in efficiently connecting semiconductor chips to redistribution circuit structures, leading to issues with signal transmission, power supply, and grounding, which affects the reliability and yield of 3D packaging and 3DIC devices.
Innovation Solution
A package structure that includes a semiconductor chip encapsulated in an insulating material with a redistribution circuit structure featuring alternating inter-dielectric and metallization layers, where the connecting pads are electrically connected to the metallization layers and conductive elements, and the metallization layers have non-planar edges with complementary shapes to reduce stress on inter-layer dielectric layers, enhancing durability and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging technologies are used to connect semiconductor chips to redistribution circuit structures, then manufacturing simplicity is maintained, but electrical connection reliability and signal transmission quality deteriorate
Solution Approach 1:
The packaging structure is divided into distinct functional layers including semiconductor chip, insulating encapsulation layer, redistribution circuit structure with alternating inter-dielectric and metallization layers. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall reliability.
Solution Approach 2:
The patent transitions from conventional 2D planar connections to a 3D stacked architecture with vertical interconnections through the insulating encapsulation layer. This dimensional change enables improved electrical connection reliability by creating multiple connection pathways and reducing signal interference.
2Strength
If planar metallization layers are used in redistribution circuit structures, then manufacturing is simpler, but mechanical stress on inter-layer dielectric layers increases reducing durability
Solution Approach 1:
The metallization layers are designed with non-planar edges featuring complementary shapes that interlock with corresponding features in adjacent layers. This asymmetric design distributes mechanical stress more evenly across the inter-layer dielectric layers, improving structural durability while remaining manufacturable through standard lithography and etching processes.
Solution Approach 2:
The metallization layers exhibit varying local properties with non-planar edges in specific regions to manage stress concentration, while maintaining planar regions for electrical connectivity. This localized modification of geometry optimizes mechanical stability without significantly complicating the overall manufacturing process.
3Productivity
If simple connecting pad structures are used, then manufacturing is easier, but signal transmission quality and power supply efficiency deteriorate
Solution Approach 1:
The connecting pads are segmented into multiple metallization layers with alternating inter-dielectric layers, creating a distributed connection structure. This segmentation improves signal transmission quality by reducing impedance and enhancing power distribution while maintaining manufacturing efficiency through standard multi-layer fabrication processes.
Data Source
AI summary
A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip.