Semiconductor Package Redistribution Layer Void Prevention
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Solution Overview
Problem
Semiconductor packages face challenges in achieving structural stability due to increasing miniaturization and higher processing speeds, leading to issues with connection reliability and void formation between the redistribution layer and the semiconductor chip.
Innovation Solution
The semiconductor package incorporates a redistribution layer with first and second patterns, a passivation layer, and a mold layer, where the second patterns act as dummy patterns electrically insulated from the semiconductor chip, enhancing structural stability and preventing void formation by ensuring a flat passivation surface for easier mold layer integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect pads of semiconductor chips to external substrates, then connection flexibility is maintained, but connection reliability deteriorates due to increasing miniaturization and processing speeds
Solution Approach 1:
The patent extracts the bonding wire from the connection structure and replaces it with direct bump connections. The semiconductor chip is equipped with connection bumps that directly contact the substrate, eliminating the intermediate wire bonding step and improving reliability through direct electrical and mechanical contact.
Solution Approach 2:
The patent introduces a redistribution layer as an intermediary structure between the semiconductor chip and substrate. This redistribution layer contains connection bumps that facilitate direct contact connections, serving as a mediator that enables reliable connections while accommodating miniaturization requirements.
2Reliability
If connection bumps are used to directly connect semiconductor chips to substrates, then connection reliability improves, but void formation increases between the redistribution layer and semiconductor chip
Solution Approach 1:
The patent applies preliminary action by forming a mold layer between the redistribution layer and semiconductor chip before final assembly. This mold layer is prepared in advance to prevent void formation during the connection process, addressing the harmful effect before it can occur.
Solution Approach 2:
The mold layer serves as a cushioning element that prevents void formation between the redistribution layer and semiconductor chip. By placing this protective layer beforehand, the patent cushions against the harmful effect of void formation during connection bump contact.
3Ease of manufacture
If the passivation layer surface is uneven, then manufacturing simplicity is maintained, but mold layer integration becomes difficult and air gaps increase
Solution Approach 1:
The patent applies local quality by selectively positioning the second patterns (dummy patterns) in specific regions of the redistribution layer. These dummy patterns are placed in areas where they can locally adjust the surface profile of the passivation layer, creating a flatter surface in critical regions for mold layer integration while maintaining manufacturing simplicity overall.
Data Source
AI summary
A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.