Semiconductor Package Multi-Layer Redistribution for High Integration Density
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Solution Overview
Problem
In semiconductor packages, the increasing number of electrical connection pads and interconnection lines in package-on-package configurations faces challenges in reducing the area and width of the backside connection pads and interconnection lines, leading to technical limitations in achieving higher integration density and reliability.
Innovation Solution
A semiconductor package design incorporating a second redistribution layer with a redistribution pad and an electrical connection structure, including a conductor layer of nickel and a contact layer of gold, which allows for a wider electrical connection pad exposed through a passivation layer, enabling denser redistribution patterns without spatial limitations, thereby improving integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of electrical connection pads and interconnection lines is increased to handle high-capacity data in package-on-package configuration, then data processing capacity is improved, but the area and width of backside connection pads and interconnection lines cannot be reduced due to standardized size requirements
Solution Approach 1:
The patent introduces a second redistribution layer above the first redistribution layer, transitioning from a single-plane to a multi-layer architecture. This vertical dimensionality change allows electrical connection pads to be stacked in multiple layers, increasing the number of connection pads without increasing the planar area of each individual pad, thus resolving the contradiction between pad quantity and pad area.
Solution Approach 2:
The patent implements a nested structure where the second redistribution layer is positioned above and connected to the first redistribution layer through vertical connection structures. This nesting arrangement allows multiple redistribution layers to occupy overlapping or adjacent spatial regions, effectively increasing connection density without proportionally increasing the overall package area.
2Productivity
If the width and space of backside interconnection lines are decreased to improve integration density, then area utilization is improved, but technical limitations prevent further reduction due to standardized pad size requirements
Solution Approach 1:
By adding a vertical dimension with multiple redistribution layers, the patent allows interconnection paths to extend in the vertical direction rather than being confined to a single plane. This enables more compact lateral spacing of interconnection lines while maintaining sufficient signal integrity and manufacturing tolerances, thereby improving integration density without excessively reducing line width.
Solution Approach 2:
The patent divides the redistribution function into multiple separate layers (first redistribution layer and second redistribution layer), each handling specific routing tasks. This segmentation allows for optimized line width and spacing in each layer independently, improving overall integration density by distributing interconnection demands across multiple segments rather than concentrating them in a single layer.
3Quantity of substance
If a second redistribution layer is added to improve integration density, then the number of electrical connections is increased, but the device complexity increases due to additional layers and structures
Solution Approach 1:
The second redistribution layer serves multiple functions simultaneously: it provides additional electrical connection pads for high-capacity data processing, enables vertical interlayer connections for three-dimensional integration, and offers additional routing paths for signal distribution. This multi-functionality justifies the increased device complexity by delivering multiple benefits from a single structural addition.
Solution Approach 2:
The patent combines the functions of multiple redistribution operations into an integrated multi-layer structure, where the first and second redistribution layers work together as a unified system. By merging these functions into a coordinated multi-layer architecture rather than separate independent structures, the patent reduces overall complexity while achieving the desired increase in electrical connection capacity.
Data Source
AI summary
A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member on the redistribution substrate, a second redistribution layer on an upper surface of the first molding member and having a redistribution pad, an electrical connection pad on an upper surface of a second molding member and electrically connected to the second redistribution layer, and a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer, including a first metal, and a contact layer on the conductor layer and including a second metal. The redistribution pad includes a third metal, different from the first metal and the second metal. The portion of the electrical connection pad, exposed by the opening, has a width greater than a width of the redistribution pad.