Semiconductor Package Redistribution Layer Via Integration
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Solution Overview
Problem
Current semiconductor package manufacturing techniques face challenges in reducing the size and increasing the integration density of semiconductor chips, particularly due to limitations in forming thin packages with printed circuit boards and achieving short signal paths.
Innovation Solution
The solution involves forming conductive vias in a silicon substrate with through holes to decrease distances between them, eliminating the need for a carrier wafer and enabling the formation of redistribution layers that connect upper and lower semiconductor chips, thereby creating a high-performance semiconductor package with reduced size and increased integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a printed circuit board is used to mount semiconductor chips, then the package can be manufactured using conventional techniques, but the package thickness cannot be reduced and integration density is limited
Solution Approach 1:
The patent extracts and eliminates the printed circuit board from the package structure, replacing it with a substrate that integrates the mounting function directly into the package body. This removal of the external PCB enables thin-profile packages while maintaining chip mounting capability through direct attachment to the substrate's upper surface.
Solution Approach 2:
The patent merges the functions of the printed circuit board and the package substrate into a single integrated structure. The substrate serves both as the mechanical support for mounting chips and as the interconnection medium through conductive vias, eliminating the need for separate PCB layers and reducing overall package thickness.
2Quantity of substance
If the distance between through electrodes is reduced to increase integration density, then more chips can be mounted in a smaller area, but the manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive vias that extend through the substrate thickness, enabling electrical interconnection in the Z-direction. This three-dimensional via structure allows chips to be densely packed in the XY-plane while maintaining electrical connectivity through the substrate thickness, increasing integration density without proportionally increasing manufacturing difficulty.
3Quantity of substance
If signal paths are lengthened to connect multiple chips, then more chips can be integrated, but signal transmission performance deteriorates
Solution Approach 1:
The patent implements local quality by providing dedicated conductive via pathways for each chip interconnection, optimizing the signal path length and routing for each specific connection. This localized via structure ensures that signal transmission paths remain as short as possible between adjacent chips, maintaining high-speed signal integrity while supporting multiple chip integration.
Data Source
AI summary
A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.