Semiconductor Package Redistribution Layer Via Interface Roughness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages face reliability issues due to thermal stress between dissimilar materials, leading to defects such as delamination and cracks, which compromise their performance and longevity.
Innovation Solution
The semiconductor package incorporates a redistribution layer with a seed layer and a plating layer on an insulating layer, featuring a first uneven surface with a surface roughness of 30 nm or more, enhancing the bonding strength between the via and the insulating layer, and between the seed and plating layers, to mitigate thermal stress-induced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redistribution layer is formed between dissimilar materials, then electrical connection is achieved, but thermal stress causes delamination and reduces reliability
Solution Approach 1:
The patent applies local quality by creating an uneven surface with specific roughness (30 nm or more) at the interface between the insulating layer and the via. This localized surface modification enhances bonding strength precisely where thermal stress concentrates, without affecting other regions of the package structure.
Solution Approach 2:
The patent changes the surface roughness parameter of the insulating layer interface to 30 nm or more. This parameter modification increases the bonding strength between dissimilar materials, enabling the structure to withstand thermal stress while maintaining electrical connectivity.
2Strength
If a via is formed through the insulating layer, then electrical connection is established, but bonding strength decreases due to smooth interface
Solution Approach 1:
The patent applies local quality by creating an uneven surface with specific roughness (30 nm or more) at the interface between the insulating layer and the via. This localized surface modification enhances bonding strength precisely where thermal stress concentrates, without affecting other regions of the package structure.
Solution Approach 2:
The patent changes the surface roughness parameter of the insulating layer interface to 30 nm or more. This parameter modification increases the bonding strength between dissimilar materials, enabling the structure to withstand thermal stress while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly improves the reliability of the semiconductor package by increasing the bonding strength and reducing the occurrence of defects like delamination, thereby enhancing its thermal and electrical performance.
Implementation Method 1
an interface between the at least one insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more
Data Source
AI summary
A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.