Semiconductor Package Redistribution Layer Via Size Reduction
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Solution Overview
Problem
Current semiconductor package technologies face challenges in reducing the size of vias and optimizing the structure to accommodate high-performance, high-speed, and compact electronic systems, particularly in efficiently connecting semiconductor chips and redistribution layers.
Innovation Solution
A method is introduced that involves forming a lower redistribution layer, bonding a stack to it, stacking a semiconductor chip, and creating an upper redistribution layer, which allows for the reduction of via size and enhances electrical connectivity through a chip-last process, using insulating layers and conductive materials to redistribute pads and terminals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor package technologies are used, then the structure is simple and easy to manufacture, but the via size cannot be reduced and the package size is large
Solution Approach 1:
The package structure is segmented into multiple functional layers including lower redistribution layer, stack structure with insulating layers and vias, semiconductor chip, and upper redistribution layer. This segmentation allows independent optimization of each layer to reduce overall package size while maintaining manufacturability
Solution Approach 2:
The patent transitions from planar 2D layout to 3D vertical stacking by introducing multiple insulating layers (first insulating layer, second insulating layer) and vias that penetrate through these layers. This dimensional change enables reduced via size and compact package footprint
2Volume of moving object
If via size is reduced for compact design, then package size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The first and second insulating layers are formed beforehand to define via locations and dimensions before via formation. This preliminary structuring establishes precise via positioning and sizing, reducing manufacturing precision requirements despite small via dimensions
Solution Approach 2:
The patent changes material parameters by introducing specific insulating layers with controlled dielectric properties and thicknesses. These parameter changes enable precise via dimension control and reduce sensitivity to manufacturing variations
3Productivity
If chip-last process is used, then production yield improves, but process complexity increases
Solution Approach 1:
The chip-last process segments the manufacturing into distinct phases: forming lower redistribution layer and stack structure separately, then bonding the semiconductor chip afterward. This segmentation enables independent qualification and optimization of each component, improving production yield despite increased process steps
Solution Approach 2:
The lower redistribution layer and stack structure are formed in advance before chip bonding. This preliminary action allows these components to be manufactured and qualified independently, improving overall production yield by enabling early defect detection and replacement
Data Source
AI summary
A method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer, and forming an upper re-distribution layer on the semiconductor chip and the stack.